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Recent questions tagged gate1996
6
votes
1
answer
1
GATE CSE 1996 | Question: 24-b
Consider the synchronous sequential circuit in the below figure Given that the initial state of the circuit is $S_4,$ identify the set of states, which are not reachable.
Consider the synchronous sequential circuit in the below figureGiven that the initial state of the circuit is $S_4,$ identify the set of states, which are not reachable.
go_editor
2.3k
views
go_editor
asked
Feb 10, 2018
Digital Logic
gate1996
normal
digital-logic
circuit-output
descriptive
+
–
35
votes
2
answers
2
GATE CSE 1996 | Question: 27
A library relational database system uses the following schema USERS (User#, User Name, Home Town) BOOKS (Book#, Book Title, Author Name) ISSUED (Book#, User#, Date) Explain in one English sentence, what each of the following relational algebra queries is ...
A library relational database system uses the following schemaUSERS (User#, User Name, Home Town)BOOKS (Book#, Book Title, Author Name)ISSUED (Book#, User#, Date)Explain ...
Kathleen
5.3k
views
Kathleen
asked
Oct 9, 2014
Databases
gate1996
databases
relational-algebra
descriptive
+
–
36
votes
5
answers
3
GATE CSE 1996 | Question: 26
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: ... of less than $100 nsec$? What is the average access time achieved using the chosen sizes of level $1$ and level $2$ memories?
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below:$$\overset{ \text {Level $1$ (Cache memory)} \\ \text{Access time = ...
Kathleen
14.9k
views
Kathleen
asked
Oct 9, 2014
CO and Architecture
gate1996
co-and-architecture
cache-memory
normal
+
–
33
votes
4
answers
4
GATE CSE 1996 | Question: 25
A hard disk is connected to a $50$ MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes $1000$ clock cycles for the processor, and assume that the handling of the interrupt at DMA completion requires $500$ ... What fraction of the processor time is consumed by the disk, if the disk is actively transferring $100\%$ of the time?
A hard disk is connected to a $50$ MHz processor through a DMA controller. Assume that the initial set-up of a DMA transfer takes $1000$ clock cycles for the processor, ...
Kathleen
10.1k
views
Kathleen
asked
Oct 9, 2014
CO and Architecture
gate1996
co-and-architecture
io-handling
dma
numerical-answers
normal
+
–
18
votes
2
answers
5
GATE CSE 1996 | Question: 24-a
Consider the synchronous sequential circuit in the below figure Draw a state diagram, which is implemented by the circuit. Use the following names for the states corresponding to the values of flip-flops as given below. ... $} \\\hline \end{array}$
Consider the synchronous sequential circuit in the below figureDraw a state diagram, which is implemented by the circuit. Use the following names for the states correspon...
Kathleen
6.4k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
circuit-output
normal
descriptive
+
–
38
votes
2
answers
6
GATE CSE 1996 | Question: 23
A file system with a one-level directory structure is implemented on a disk with disk block size of $4K$ ... What is the maximum possible number of files? What is the maximum possible file size in blocks
A file system with a one-level directory structure is implemented on a disk with disk block size of $4K$ bytes. The disk is used as follows:$$\begin{array}{|l|}\hline \te...
Kathleen
9.8k
views
Kathleen
asked
Oct 9, 2014
Operating System
gate1996
operating-system
disk
normal
file-system
descriptive
+
–
22
votes
3
answers
7
GATE CSE 1996 | Question: 22
A computer system uses the Banker's Algorithm to deal with deadlocks. Its current state is shown in the table below, where $P0$, $P1$, $P2$ are processes, and $R0$, $R1$, $R2$ ... the system can be in this state What will the system do on a request by process $P0$ for one unit of resource type $R1$?
A computer system uses the Banker’s Algorithm to deal with deadlocks. Its current state is shown in the table below, where $P0$, $P1$, $P2$ are processes, and $R0$, $R1...
Kathleen
8.9k
views
Kathleen
asked
Oct 9, 2014
Operating System
gate1996
operating-system
resource-allocation
normal
descriptive
+
–
34
votes
1
answer
8
GATE CSE 1996 | Question: 21
The concurrent programming constructs fork and join are as below: Fork <label> which creates a new process executing from the specified label Join <variable> which decrements the specified synchronization variable (by $1$) and terminates the process if the new value is not $0$. Show ... $N$ $S3$ $L2$ : join $M$ $S5$ $L3:S2$ Goto $L1$ $L4:S4$ Goto $L2$ Next:
The concurrent programming constructs fork and join are as below:Fork <label which creates a new process executing from the specified labelJoin <variable which decrements...
Kathleen
6.1k
views
Kathleen
asked
Oct 9, 2014
Operating System
gate1996
operating-system
process-synchronization
normal
descriptive
+
–
18
votes
2
answers
9
GATE CSE 1996 | Question: 20
Consider the syntax-directed translation schema (SDTS) shown below: $E\rightarrow E + E$ {print + } $E\rightarrow E * E$ {print . } $E\rightarrow id$ {print id.name} $E\rightarrow (E)$ An LR-parser executes the actions associated with ... corresponding production. Draw the parse tree and write the translation for the sentence. $(a+b)*(c+d)$, using SDTS given above.
Consider the syntax-directed translation schema (SDTS) shown below:$E\rightarrow E + E$ {print “+”}$E\rightarrow E * E$ {print “.”}$E\rightarrow id$ {print id.nam...
Kathleen
3.4k
views
Kathleen
asked
Oct 9, 2014
Compiler Design
gate1996
compiler-design
syntax-directed-translation
normal
descriptive
+
–
3
votes
1
answer
10
GATE CSE 1996 | Question: 19
Consider the following program in pseudo-Pascal syntax. What is printed by the program if parameter $a$ in procedure $\text{test1}$ is passed as call-by-reference parameter call-by-value-result parameter program Example (input, output) var b: integer; procedure test2: begin b ... ', a, b); end begin (*Example*) b:=3; test1(b); writeln('point3: ', b); end
Consider the following program in pseudo-Pascal syntax. What is printed by the program if parameter $a$ in procedure $\text{test1}$ is passed ascall-by-reference paramete...
Kathleen
1.5k
views
Kathleen
asked
Oct 9, 2014
Programming in C
gate1996
programming
parameter-passing
normal
out-of-syllabus-now
+
–
24
votes
2
answers
11
GATE CSE 1996 | Question: 18
Consider the following program that attempts to locate an element $x$ in an array $a[ ]$ using binary search. Assume $N > 1$. The program is erroneous. Under what conditions does the program fail? var i,j,k: integer; x: integer; a: array; [1..N] of ... ; if (a[k] = x) then writeln ('x is in the array') else writeln ('x is not in the array') end;
Consider the following program that attempts to locate an element $x$ in an array $a[ ]$ using binary search. Assume $N 1$. The program is erroneous. Under what conditio...
Kathleen
3.4k
views
Kathleen
asked
Oct 9, 2014
Algorithms
gate1996
algorithms
searching
normal
descriptive
+
–
25
votes
7
answers
12
GATE CSE 1996 | Question: 17
Let $G$ be the directed, weighted graph shown in below figure We are interested in the shortest paths from $A$. Output the sequence of vertices identified by the Dijkstra's algorithm for single source shortest path when the algorithm is started at node $A$ Write down ... vertices in the shortest path from $A$ to $E$ What is the cost of the shortest path from $A$ to $E$?
Let $G$ be the directed, weighted graph shown in below figureWe are interested in the shortest paths from $A$.Output the sequence of vertices identified by the Dijkstra�...
Kathleen
7.4k
views
Kathleen
asked
Oct 9, 2014
Algorithms
gate1996
algorithms
graph-algorithm
normal
dijkstras-algorithm
descriptive
+
–
26
votes
1
answer
13
GATE CSE 1996 | Question: 16
A complete, undirected, weighted graph $G$ is given on the vertex $\{0, 1,\dots, n -1\}$ for any fixed ‘n’. Draw the minimum spanning tree of $G$ if the weight of the edge $(u, v)$ is $\mid u-v\mid$ the weight of the edge $(u, v)$ is $u + v$
A complete, undirected, weighted graph $G$ is given on the vertex $\{0, 1,\dots, n -1\}$ for any fixed ‘n’. Draw the minimum spanning tree of $G$ ifthe weight of the ...
Kathleen
5.1k
views
Kathleen
asked
Oct 9, 2014
Algorithms
gate1996
algorithms
graph-algorithms
spanning-tree
normal
descriptive
+
–
24
votes
4
answers
14
GATE CSE 1996 | Question: 15
Insert the characters of the string $K \ R \ P \ C \ S \ N \ Y \ T \ J \ M$ into a hash table of size $10$. Use the hash function $h(x)=( ord (x) – ord (\text{“}a\text{”}) + 1) \mod 10$ and linear probing to resolve collisions. Which insertions cause collisions? Display the final hash table.
Insert the characters of the string $K \ R \ P \ C \ S \ N \ Y \ T \ J \ M$ into a hash table of size $10$.Use the hash function$$h(x)=( ord (x) – ord (\text{“}a\tex...
Kathleen
6.1k
views
Kathleen
asked
Oct 9, 2014
DS
gate1996
data-structures
hashing
normal
descriptive
+
–
35
votes
2
answers
15
GATE CSE 1996 | Question: 14
A two dimensional array $A[1..n][1..n]$ of integers is partially sorted if $\forall i, j\in [1..n-1], A[i][j] < A[i][j+1] \text{ and } A[i][j] < A[i+1][j]$ The smallest item in the array is at $A[i][j]$ where $i=\_\_$ and $j=\_\_$. The smallest ... if A[i+1][j] < A[i][j] ___ then begin A[i][j]:=A[i+1][j]; i:=i+1; end else begin _____ end A[i][j]:= ____ end
A two dimensional array $A[1..n][1..n]$ of integers is partially sorted if $\forall i, j\in [1..n-1], A[i][j] < A[i][j+1] \text{ and } A[i][j] < A[i+1][j]$The smallest it...
Kathleen
5.7k
views
Kathleen
asked
Oct 9, 2014
Algorithms
gate1996
algorithms
sorting
normal
descriptive
+
–
17
votes
2
answers
16
GATE CSE 1996 | Question: 13
Let $Q=\left( \left\{q_1,q_2 \right\}, \left\{a,b\right \}, \left\{a,b,\bot \right\}, \delta, \bot, \phi \right)$ ... $\delta(q_2,b,b) = \left\{(q_2, \epsilon)\right\}$ $\delta(q_2,\epsilon,\bot) = \left\{(q_2, \epsilon)\right\}$
Let $Q=\left( \left\{q_1,q_2 \right\}, \left\{a,b\right \}, \left\{a,b,\bot \right\}, \delta, \bot, \phi \right)$ be a pushdown automaton accepting by empty stack for the...
Kathleen
5.5k
views
Kathleen
asked
Oct 9, 2014
Theory of Computation
gate1996
theory-of-computation
pushdown-automata
normal
descriptive
+
–
40
votes
1
answer
17
GATE CSE 1996 | Question: 12
Given below are the transition diagrams for two finite state machines $M_1$ and $M_2$ recognizing languages $L_1$ and $L_2$ respectively. Display the transition diagram for a machine that recognizes $L_1.L_2$, obtained from transition diagrams for $M_1$ ... $\varepsilon$ transitions and no new states. (Final states are enclosed in double circles).
Given below are the transition diagrams for two finite state machines $M_1$ and $M_2$ recognizing languages $L_1$ and $L_2$ respectively.Display the transition diagram fo...
Kathleen
8.3k
views
Kathleen
asked
Oct 9, 2014
Theory of Computation
gate1996
theory-of-computation
finite-automata
normal
descriptive
+
–
34
votes
5
answers
18
GATE CSE 1996 | Question: 11
Let $G$ be a context-free grammar where $G=(\{S, A, B, C\}, \{a, b, d\}, P, S)$ with the productions in $P$ given below. $S \rightarrow ABAC$ $A \rightarrow aA \mid \varepsilon$ $B \rightarrow bB \mid \varepsilon$ ... $\varepsilon$ productions and no unit productions. (A unit production is of the form $x \rightarrow y$, and $x$ and $y$ are non terminals).
Let $G$ be a context-free grammar where $G=(\{S, A, B, C\}, \{a, b, d\}, P, S)$ with the productions in $P$ given below.$S \rightarrow ABAC$$A \rightarrow aA \mid \vareps...
Kathleen
7.6k
views
Kathleen
asked
Oct 9, 2014
Compiler Design
gate1996
compiler-design
grammar
normal
descriptive
+
–
14
votes
4
answers
19
GATE CSE 1996 | Question: 10
Let $A = \begin{bmatrix} a_{11} && a_{12} \\ a_{21} && a_{22} \end{bmatrix} \text { and } B = \begin{bmatrix} b_{11} && b_{12} \\ b_{21} && b_{22} \end{bmatrix}$ be two matrices such that $AB=I$ ... $CD =I$. Express the elements of $D$ in terms of the elements of $B$.
Let $A = \begin{bmatrix} a_{11} && a_{12} \\ a_{21} && a_{22} \end{bmatrix} \text { and } B = \begin{bmatrix} b_{11} && b_{12} \\ b_{21} && b_{22} \end{bmatrix}$ be two m...
Kathleen
4.0k
views
Kathleen
asked
Oct 9, 2014
Linear Algebra
gate1996
linear-algebra
matrix
normal
descriptive
+
–
6
votes
1
answer
20
GATE CSE 1996 | Question: 9
The Fibonacci sequence $\{f_1, f_2, f_3 \ldots f_n\}$ is defined by the following recurrence:$f_{n+2} = f_{n+1} + f_n, n \geq 1; f_2 =1:f_1=1$Prove by induction that every third element of the sequence is even.
The Fibonacci sequence $\{f_1, f_2, f_3 \ldots f_n\}$ is defined by the following recurrence:$$f_{n+2} = f_{n+1} + f_n, n \geq 1; f_2 =1:f_1=1$$Prove by induction that ev...
Kathleen
1.3k
views
Kathleen
asked
Oct 9, 2014
Combinatory
gate1996
recurrence-relation
proof
descriptive
+
–
41
votes
5
answers
21
GATE CSE 1996 | Question: 8
Let $F$ be the collection of all functions $f: \{1, 2, 3\} \to \{1, 2, 3\}$. If $f$ and $g \in F$, define an equivalence relation $\sim$ by $f\sim g$ if and only if $f(3) = g(3)$. Find the number of equivalence classes defined by $\sim$. Find the number of elements in each equivalence class.
Let $F$ be the collection of all functions $f: \{1, 2, 3\} \to \{1, 2, 3\}$. If $f$ and $g \in F$, define an equivalence relation $\sim$ by $f\sim g$ if and only if $f(3)...
Kathleen
5.9k
views
Kathleen
asked
Oct 9, 2014
Set Theory & Algebra
gate1996
set-theory&algebra
relations
functions
normal
descriptive
+
–
34
votes
2
answers
22
GATE CSE 1996 | Question: 7
A demand paged virtual memory system uses $16$ bit virtual address, page size of $256$ bytes, and has $1$ Kbyte of main memory. $\text{LRU}$ page replacement is implemented using the list, whose current status (page number is decimal) is For each ... indicate the new status of the list page faults, if any, and page replacements, if any.
A demand paged virtual memory system uses $16$ bit virtual address, page size of $256$ bytes, and has $1$ Kbyte of main memory. $\text{LRU}$ page replacement is implement...
Kathleen
7.8k
views
Kathleen
asked
Oct 9, 2014
Operating System
gate1996
operating-system
virtual-memory
normal
descriptive
+
–
0
votes
1
answer
23
GATE CSE 1996 | Question: 6
An 8052 based system has an output port with address 00H. Consider the following assembly language program. ORG 0100H MVI A, 00H LXI H, 0105H OUT 00H INR A PCHL HLT What does the program do with respect to the output port $00H$ ? Show the waveforms at the three least significant bits of the port $00H$.
An 8052 based system has an output port with address 00H. Consider the following assembly language program.ORG 0100H MVI A, 00H LXI H, 0105H OUT 00H INR A PCHL HLTWhat do...
Kathleen
792
views
Kathleen
asked
Oct 9, 2014
CO and Architecture
gate1996
co-and-architecture
8085-microprocessor
out-of-syllabus-now
+
–
17
votes
1
answer
24
GATE CSE 1996 | Question: 5
A logic network has two data inputs $A$ and $B$, and two control inputs $C_0$ and $C_1$. It implements the function $F$ according to the following table. ${\begin{array}{|cc|c|}\hline \textbf{$C_1$}& \textbf{$ ... $1$ Multiplexer, one $2-$input Exclusive OR gate, one $2-$input AND gate, one $2-$input OR gate and one Inverter.
A logic network has two data inputs $A$ and $B$, and two control inputs $C_0$ and $C_1$. It implements the function $F$ according to the following table.$${\begin{array}{...
Kathleen
4.1k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
normal
digital-circuits
descriptive
+
–
54
votes
7
answers
25
GATE CSE 1996 | Question: 4
A binary search tree is used to locate the number $43$ ...
A binary search tree is used to locate the number $43$. Which of the following probe sequences are possible and which are not? Explain.$\begin{array}{llllll} \text{(a)} ...
Kathleen
22.7k
views
Kathleen
asked
Oct 9, 2014
DS
gate1996
data-structures
binary-search-tree
normal
descriptive
+
–
27
votes
2
answers
26
GATE CSE 1996 | Question: 3
Let $f$ be a function defined by $f(x) = \begin{cases} x^2 &\text{ for }x \leq 1\\ ax^2+bx+c &\text{ for } 1 < x \leq 2 \\ x+d &\text{ for } x>2 \end{cases}$ Find the values for the constants $a$, $b$, $c$ and $d$ so that $f$ is continuous and differentiable everywhere on the real line.
Let $f$ be a function defined by$$f(x) = \begin{cases} x^2 &\text{ for }x \leq 1\\ ax^2+bx+c &\text{ for } 1 < x \leq 2 \\ x+d &\text{ for } x>2 \end{cases}$$Find the va...
Kathleen
5.2k
views
Kathleen
asked
Oct 9, 2014
Calculus
gate1996
calculus
continuity
differentiation
normal
descriptive
+
–
33
votes
6
answers
27
GATE CSE 1996 | Question: 2.25
A micro program control unit is required to generate a total of $25$ control signals. Assume that during any micro instruction, at most two control signals are active. Minimum number of bits required in the control word to generate the required control signals will be: $2$ $2.5$ $10$ $12$
A micro program control unit is required to generate a total of $25$ control signals. Assume that during any micro instruction, at most two control signals are active. Mi...
Kathleen
24.6k
views
Kathleen
asked
Oct 9, 2014
CO and Architecture
gate1996
co-and-architecture
microprogramming
normal
+
–
19
votes
4
answers
28
GATE CSE 1996 | Question: 2.24
What is the equivalent Boolean expression in product-of-sums form for the Karnaugh map given in Fig $B\overline{D} + \overline{B}D$ $(B + \overline{C} +D) (\overline{B} + C + \overline{D})$ $(B + {D})(\overline{B} +\overline{ D})$ $(B + \overline{D})(\overline{B} + {D})$
What is the equivalent Boolean expression in product-of-sums form for the Karnaugh map given in Fig $B\overline{D} + \overline{B}D$$(B + \overline{C} +D) (\overline{B} + ...
Kathleen
9.0k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
k-map
easy
+
–
40
votes
5
answers
29
GATE CSE 1996 | Question: 2.23
Consider the following state table for a sequential machine. The number of states in the minimized machine will be ... $4$ $3$ $2$ $1$
Consider the following state table for a sequential machine. The number of states in the minimized machine will be$$\begin{array}{|l|l|ll|}\hline \text{} & \text{} & \tex...
Kathleen
12.8k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
normal
finite-automata
+
–
24
votes
2
answers
30
GATE CSE 1996 | Question: 2.22
Consider the circuit in figure. $f$ implements $\overline{A} \overline{B}C + \overline{A}B \overline{C} + ABC$ $A + B + C$ $A \oplus B \oplus C$ $AB + BC + CA$
Consider the circuit in figure. $f$ implements$\overline{A} \overline{B}C + \overline{A}B \overline{C} + ABC$$A + B + C$$A \oplus B \oplus C$$AB + BC + CA$
Kathleen
8.4k
views
Kathleen
asked
Oct 9, 2014
Digital Logic
gate1996
digital-logic
circuit-output
easy
multiplexer
+
–
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