Recent questions tagged gate2005-cse

24 votes

2 answers

1

GATE CSE 2005 | Question: 83b
Consider the following expression grammar. The semantic rules for expression evaluation are stated next to each grammar production. ... of $+$' is higher than that of $\times$', and both operators are left associative; expression is evaluated to $9$

Consider the following expression grammar. The semantic rules for expression evaluation are stated next to each grammar production. ... to $7$ Precedence of $+$' is higher than that of $\times$', and both operators are left associative; expression is evaluated to $9$

asked Nov 27, 2016 in Compiler Design jothee 6.4k views

21 votes

3 answers

2

GATE CSE 2005 | Question: 84b
We are given $9$ tasks $T_1, T_2, \dots, T_9$. The execution of each task requires one unit of time. We can execute one task at a time. Each task $T_i$ has a profit $P_i$ and a deadline $d_i$. Profit $P_i$ is earned if the task is completed before the end ... $} & \text{$3$} \\\hline \end{array}$ What is the maximum profit earned? $147$ $165$ $167$ $175$

We are given $9$ tasks $T_1, T_2, \dots, T_9$. The execution of each task requires one unit of time. We can execute one task at a time. Each task $T_i$ has a profit $P_i$ and a deadline $d_i$. Profit $P_i$ is earned if the task is completed before the end of the $d_i^{th}$ unit ... $} & \text{$7$} & \text{$3$} \\\hline \end{array}$ What is the maximum profit earned? $147$ $165$ $167$ $175$

asked Nov 15, 2016 in Algorithms jothee 2.2k views

25 votes

5 answers

3

GATE CSE 2005 | Question: 81b
double foo(int n) { int i; double sum; if(n == 0) { return 1.0; } else { sum = 0.0; for(i = 0; i < n; i++) { sum += foo(i); } return sum; } } Suppose we modify the above function $foo()$ ... time complexity for function $foo()$ is significantly reduced. The space complexity of the modified function would be: $O(1)$ $O(n)$ $O(n^2)$ $n!$

double foo(int n) { int i; double sum; if(n == 0) { return 1.0; } else { sum = 0.0; for(i = 0; i < n; i++) { sum += foo(i); } return sum; } } Suppose we modify the above function $foo()$ ... modification the time complexity for function $foo()$ is significantly reduced. The space complexity of the modified function would be: $O(1)$ $O(n)$ $O(n^2)$ $n!$

asked Nov 14, 2016 in Programming jothee 5.3k views

24 votes

3 answers

4

GATE CSE 2005 | Question: 85-b
Consider the following floating-point format. Mantissa is a pure fraction in sign-magnitude form. The normalized representation for the above format is specified as follows. The mantissa has an implicit $1$ preceding the binary (radix) point. Assume that only $0's$ are padded in while ... above number $(0.239 \times 2^{13})$ is: $0A\;20$ $11\;34$ $49\;D0$ $4A\;E8$

Consider the following floating-point format. Mantissa is a pure fraction in sign-magnitude form. The normalized representation for the above format is specified as follows. The mantissa has an implicit $1$ preceding the binary (radix) point. Assume that only $0's$ are padded in while shifting a field. The ... of the above number $(0.239 \times 2^{13})$ is: $0A\;20$ $11\;34$ $49\;D0$ $4A\;E8$

asked Nov 14, 2016 in Digital Logic jothee 4k views

34 votes

4 answers

5

GATE CSE 2005 | Question: 82b
Let $s$ and $t$ be two vertices in a undirected graph $G=(V,E)$ having distinct positive edge weights. Let $[X,Y]$ be a partition of $V$ such that $s \in X$ and $t \in Y$. Consider the edge $e$ having the minimum weight amongst all those edges ... spanning tree a weighted shortest path from $s$ to $t$ an Euler walk from $s$ to $t$ a Hamiltonian path from $s$ to $t$

Let $s$ and $t$ be two vertices in a undirected graph $G=(V,E)$ having distinct positive edge weights. Let $[X,Y]$ be a partition of $V$ such that $s \in X$ and $t \in Y$. Consider the edge $e$ having the minimum weight amongst all those edges that have one ... minimum weighted spanning tree a weighted shortest path from $s$ to $t$ an Euler walk from $s$ to $t$ a Hamiltonian path from $s$ to $t$

asked Nov 14, 2016 in Algorithms jothee 3.3k views

41 votes

12 answers

6

GATE CSE 2005 | Question: 80
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for ... ; The minimum number of CPU clock cycles needed during the execution cycle of this instruction is: $2$ $3$ $4$ $5$

The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the MAR ... $2$ $3$ $4$ $5$

asked Apr 24, 2016 in CO and Architecture jothee 13.9k views

66 votes

5 answers

7

GATE CSE 2005 | Question: 61
Consider line number $3$ of the following C-program. int main() { /*Line 1 */ int I, N; /*Line 2 */ fro (I=0, I<N, I++); /*Line 3 */ } Identify the compiler’s response about this line while creating the object-module: No compilation error Only a lexical error Only syntactic errors Both lexical and syntactic errors

Consider line number $3$ of the following C-program. int main() { /*Line 1 */ int I, N; /*Line 2 */ fro (I=0, I<N, I++); /*Line 3 */ } Identify the compiler’s response about this line while creating the object-module: No compilation error Only a lexical error Only syntactic errors Both lexical and syntactic errors

asked Nov 12, 2014 in Compiler Design Vikrant Singh 11.6k views

32 votes

3 answers

8

GATE CSE 2005 | Question: 85-a
Consider the following floating-point format. Mantissa is a pure fraction in sign-magnitude form. The decimal number 0.239 $\times$ 2$^{13}$ has the following hexadecimal representation (without normalization and rounding off): 0D 24 0D 4D 4D 0D 4D 3D

Consider the following floating-point format. Mantissa is a pure fraction in sign-magnitude form. The decimal number 0.239 $\times$ 2$^{13}$ has the following hexadecimal representation (without normalization and rounding off): 0D 24 0D 4D 4D 0D 4D 3D

asked Sep 23, 2014 in Digital Logic Kathleen 10.1k views

26 votes

4 answers

9

GATE CSE 2005 | Question: 84a
We are given $9$ tasks $T_1, T_2, \dots, T_9$. The execution of each task requires one unit of time. We can execute one task at a time. Each task $T_i$ has a profit $P_i$ and a deadline $d_i$. Profit $P_i$ is earned if the task is completed before ... profit? All tasks are completed $T_1$ and $T_6$ are left out $T_1$ and $T_8$ are left out $T_4$ and $T_6$ are left out

We are given $9$ tasks $T_1, T_2, \dots, T_9$. The execution of each task requires one unit of time. We can execute one task at a time. Each task $T_i$ has a profit $P_i$ and a deadline $d_i$. Profit $P_i$ is earned if the task is completed before the end of the ... gives maximum profit? All tasks are completed $T_1$ and $T_6$ are left out $T_1$ and $T_8$ are left out $T_4$ and $T_6$ are left out

asked Sep 23, 2014 in Algorithms Kathleen 6.8k views

44 votes

7 answers

10

GATE CSE 2005 | Question: 83a
Statement for Linked Answer Questions 83a & 83b: Consider the following expression grammar. The semantic rules for expression evaluation are stated next to each grammar production. ... a reduce action It detects shift-reduce conflict, and resolves the conflict in favor of a reduce over a shift action

Statement for Linked Answer Questions 83a & 83b: Consider the following expression grammar. The semantic rules for expression evaluation are stated next to each grammar production. ... of a shift over a reduce action It detects shift-reduce conflict, and resolves the conflict in favor of a reduce over a shift action

asked Sep 23, 2014 in Compiler Design Kathleen 12.6k views

34 votes

9 answers

11

GATE CSE 2005 | Question: 82a
Let $s$ and $t$ be two vertices in a undirected graph $G=(V,E)$ having distinct positive edge weights. Let $[X,Y]$ be a partition of $V$ such that $s \in X$ and $t \in Y$. Consider the edge $e$ having the minimum weight amongst all those edges that ... of $G$ the weighted shortest path from $s$ to $t$ each path from $s$ to $t$ the weighted longest path from $s$ to $t$

Let $s$ and $t$ be two vertices in a undirected graph $G=(V,E)$ having distinct positive edge weights. Let $[X,Y]$ be a partition of $V$ such that $s \in X$ and $t \in Y$. Consider the edge $e$ having the minimum weight amongst all those edges that have one vertex in ... tree of $G$ the weighted shortest path from $s$ to $t$ each path from $s$ to $t$ the weighted longest path from $s$ to $t$

asked Sep 22, 2014 in Algorithms Kathleen 6.5k views

42 votes

5 answers

12

GATE CSE 2005 | Question: 81a
double foo(int n) { int i; double sum; if(n == 0) { return 1.0; } else { sum = 0.0; for(i = 0; i < n; i++) { sum += foo(i); } return sum; } } The space complexity of the above code is? $O(1)$ $O(n)$ $O(n!)$ $n^n$

double foo(int n) { int i; double sum; if(n == 0) { return 1.0; } else { sum = 0.0; for(i = 0; i < n; i++) { sum += foo(i); } return sum; } } The space complexity of the above code is? $O(1)$ $O(n)$ $O(n!)$ $n^n$

asked Sep 22, 2014 in Programming Kathleen 10.7k views

37 votes

6 answers

13

GATE CSE 2005 | Question: 79
Consider the following data path of a CPU. The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory ... R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is: $2$ $3$ $4$ $5$

Consider the following data path of a CPU. The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the ... <= R0 + R1. The minimum number of clock cycles needed for execution cycle of this instruction is: $2$ $3$ $4$ $5$

asked Sep 22, 2014 in CO and Architecture Kathleen 13.1k views

19 votes

2 answers

14

GATE CSE 2005 | Question: 78
Consider a relation scheme $R = (A, B, C, D, E, H)$ on which the following functional dependencies hold: {$A \rightarrow B$, $BC \rightarrow D$, $E \rightarrow C$, $D \rightarrow A$}. What are the candidate keys R? $AE, BE$ $AE, BE, DE$ $AEH, BEH, BCH$ $AEH, BEH, DEH$

Consider a relation scheme $R = (A, B, C, D, E, H)$ on which the following functional dependencies hold: {$A \rightarrow B$, $BC \rightarrow D$, $E \rightarrow C$, $D \rightarrow A$}. What are the candidate keys R? $AE, BE$ $AE, BE, DE$ $AEH, BEH, BCH$ $AEH, BEH, DEH$

asked Sep 22, 2014 in Databases Kathleen 6.9k views

56 votes

7 answers

15

GATE CSE 2005 | Question: 77, ISRO2016-55
The relation book (title,price) contains the titles and prices of different books. Assuming that no two books have the same price, what does the following SQL query list? select title from book as B where (select count(*) from ... books Title of the fifth most inexpensive book Title of the fifth most expensive book Titles of the five most expensive books

The relation book (title,price) contains the titles and prices of different books. Assuming that no two books have the same price, what does the following SQL query list? select title from book as B where (select count(*) from book as T where T.price ... four most expensive books Title of the fifth most inexpensive book Title of the fifth most expensive book Titles of the five most expensive books

asked Sep 22, 2014 in Databases Kathleen 18.4k views

31 votes

2 answers

16

GATE CSE 2005 | Question: 76
The following table has two attributes $A$ and $C$ where $A$ is the primary key and $C$ is the foreign key referencing $A$ ... $(7, 2)$ $(5, 2), (7, 2)$ and $(9, 5)$ $(3, 4), (4, 3)$ and $(6, 4)$

The following table has two attributes $A$ and $C$ where $A$ is the primary key and $C$ is the foreign key referencing $A$ ... $(5, 2)$ and $(7, 2)$ $(5, 2), (7, 2)$ and $(9, 5)$ $(3, 4), (4, 3)$ and $(6, 4)$

asked Sep 22, 2014 in Databases Kathleen 8k views

29 votes

4 answers

17

GATE CSE 2005 | Question: 75
Let $E_1$ and $E_2$ be two entities in an $E/R$ diagram with simple-valued attributes. $R_1$ and $R_2$ are two relationships between $E_1$ and $E_2$, where $R_1$ is one-to-many and $R_2$ is many-to-many. $R_1$ and $R_2$ do not have ... of their own. What is the minimum number of tables required to represent this situation in the relational model? $2$ $3$ $4$ $5$

Let $E_1$ and $E_2$ be two entities in an $E/R$ diagram with simple-valued attributes. $R_1$ and $R_2$ are two relationships between $E_1$ and $E_2$, where $R_1$ is one-to-many and $R_2$ is many-to-many. $R_1$ and $R_2$ do not have any attributes of their own. What is the minimum number of tables required to represent this situation in the relational model? $2$ $3$ $4$ $5$

asked Sep 22, 2014 in Databases Kathleen 7k views

64 votes

7 answers

18

GATE CSE 2005 | Question: 74
Suppose the round trip propagation delay for a $10\text{ Mbps}$ Ethernet having $48\text{-bit}$ jamming signal is $46.4\ \mu s$. The minimum frame size is: $94$ $416$ $464$ $512$

Suppose the round trip propagation delay for a $10\text{ Mbps}$ Ethernet having $48\text{-bit}$ jamming signal is $46.4\ \mu s$. The minimum frame size is: $94$ $416$ $464$ $512$

asked Sep 22, 2014 in Computer Networks Kathleen 19.1k views

54 votes

8 answers

19

GATE CSE 2005 | Question: 73
In a packet switching network, packets are routed from source to destination along a single path having two intermediate nodes. If the message size is $24$ bytes and each packet contains a header of $3$ bytes, then the optimum packet size is: $4$ $6$ $7$ $9$

In a packet switching network, packets are routed from source to destination along a single path having two intermediate nodes. If the message size is $24$ bytes and each packet contains a header of $3$ bytes, then the optimum packet size is: $4$ $6$ $7$ $9$

asked Sep 22, 2014 in Computer Networks Kathleen 19k views

34 votes

4 answers

20

GATE CSE 2005 | Question: 71
Suppose $n$ processes, $P_1, \dots P_n$ share $m$ identical resource units, which can be reserved and released one at a time. The maximum resource requirement of process $P_i$ is $s_i$, where $s_i > 0$. Which one of the following is a sufficient condition for ensuring that deadlock ... $\displaystyle{\sum_{i=1}^n} \: s_i < (m \times n)$

Suppose $n$ processes, $P_1, \dots P_n$ share $m$ identical resource units, which can be reserved and released one at a time. The maximum resource requirement of process $P_i$ is $s_i$, where $s_i > 0$. Which one of the following is a sufficient condition for ensuring that deadlock does not occur? ... $\displaystyle{\sum_{i=1}^n} \: s_i < (m+n)$ $\displaystyle{\sum_{i=1}^n} \: s_i < (m \times n)$

asked Sep 22, 2014 in Operating System Kathleen 6.9k views

53 votes

11 answers

21

GATE CSE 2005 | Question: 70
Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent ... $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$

Consider a disk drive with the following specifications: $16$ surfaces, $512$ tracks/surface, $512$ sectors/track, $1$ KB/sector, rotation speed $3000$ rpm. The disk is operated in cycle stealing mode whereby whenever one $4$ byte word is ready it is sent to memory; similarly, ... is $40$ nsec. The maximum percentage of time that the CPU gets blocked during DMA operation is: $10$ $25$ $40$ $50$

asked Sep 22, 2014 in CO and Architecture Kathleen 23.6k views

40 votes

4 answers

22

GATE CSE 2005 | Question: 69
A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is ... gain of operating the device under interrupt mode over operating it under program-controlled mode? $15$ $25$ $35$ $45$

A device with data transfer rate $10$ KB/sec is connected to a CPU. Data is transferred byte-wise. Let the interrupt overhead be $4\mu$sec. The byte transfer time between the device interface register and CPU or memory is negligible. What is the minimum performance gain of operating the device under interrupt mode over operating it under program-controlled mode? $15$ $25$ $35$ $45$

asked Sep 22, 2014 in CO and Architecture Kathleen 11.1k views

113 votes

4 answers

23

GATE CSE 2005 | Question: 68
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the register read ... clock cycles taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$

asked Sep 22, 2014 in CO and Architecture Kathleen 28k views

21 votes

2 answers

24

GATE CSE 2005 | Question: 67
Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and the number of tag bits are respectively, $10, 17$ $10, 22$ $15, 17$ $5, 17$

Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and the number of tag bits are respectively, $10, 17$ $10, 22$ $15, 17$ $5, 17$

asked Sep 22, 2014 in CO and Architecture Kathleen 8.3k views

22 votes

2 answers

25

GATE CSE 2005 | Question: 66
Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.$\begin{array}{clcl} \text{(1)} &\text{$ ... $(1, b), (2, c), (3, a)$ $(1, a), (2, b), (3, c)$

Match each of the high level language statements given on the left hand side with the most natural addressing mode from those listed on the right hand side.$\begin{array}{clcl} \text{(1)} &\text{$A[I] = B[J]$} & \qquad\text{(a)} &\text{Indirect addressing} \\ \text{(2)} &\text{while $ ... $(1, c), (2, c), (3, b)$ $(1, b), (2, c), (3, a)$ $(1, a), (2, b), (3, c)$

asked Sep 22, 2014 in CO and Architecture Kathleen 3.7k views

77 votes

7 answers

26

GATE CSE 2005 | Question: 65
Consider a three word machine instruction $ADD A[R_0], @B$ The first operand (destination) $A[R_0]$ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) [email protected]$ uses indirect addressing mode. $A$ and $B$ are ... (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$

Consider a three word machine instruction $ADD A[R_0], @B$ The first operand (destination) $A[R_0]$ uses indexed addressing mode with $R_0$ as the index register. The second operand (source) [email protected]$ uses indirect addressing mode. $A$ and $B$ are memory addresses ... destination (first operand). The number of memory cycles needed during the execution cycle of the instruction is: $3$ $4$ $5$ $6$

asked Sep 22, 2014 in CO and Architecture Kathleen 20.9k views

24 votes

3 answers

27

GATE CSE 2005 | Question: 64
Consider the following circuit: The flip-flops are positive edge triggered D FFs. Each state is designated as a two-bit string $Q_0Q_1$. Let the initial state be 00. The state transition sequence is

Consider the following circuit: The flip-flops are positive edge triggered D FFs. Each state is designated as a two-bit string $Q_0Q_1$. Let the initial state be 00. The state transition sequence is

asked Sep 22, 2014 in Digital Logic Kathleen 5.2k views

26 votes

2 answers

28

GATE CSE 2005 | Question: 63
The following diagram represents a finite state machine which takes as input a binary number from the least significant bit. Which of the following is TRUE? It computes $1$’s complement of the input number It computes $2$’s complement of the input number It increments the input number it decrements the input number

The following diagram represents a finite state machine which takes as input a binary number from the least significant bit. Which of the following is TRUE? It computes $1$’s complement of the input number It computes $2$’s complement of the input number It increments the input number it decrements the input number

asked Sep 22, 2014 in Theory of Computation Kathleen 4.6k views

21 votes

1 answer

29

GATE CSE 2005 | Question: 60
Consider the grammar: $S \rightarrow (S) \mid a$ Let the number of states in SLR (1), LR(1) and LALR(1) parsers for the grammar be $n_1, n_2$ and $n_3$ respectively. The following relationship holds good: $n_1 < n_2 < n_3$ $n_1 = n_3 < n_2$ $n_1 = n_2 = n_3$ $n_1 \geq n_3 \geq n_2$

Consider the grammar: $S \rightarrow (S) \mid a$ Let the number of states in SLR (1), LR(1) and LALR(1) parsers for the grammar be $n_1, n_2$ and $n_3$ respectively. The following relationship holds good: $n_1 < n_2 < n_3$ $n_1 = n_3 < n_2$ $n_1 = n_2 = n_3$ $n_1 \geq n_3 \geq n_2$

asked Sep 22, 2014 in Compiler Design Kathleen 8k views

27 votes

5 answers

30

GATE CSE 2005 | Question: 59
Consider the grammar: $E \rightarrow E + n \mid E \times n \mid n$ For a sentence $n + n \times n$, the handles in the right-sentential form of the reduction are: $n, E + n$ and $E + n \times n$ $n, E + n$ and $E + E \times n$ $n, n + n$ and $n + n \times n$ $n, E + n$ and $E \times n$

Consider the grammar: $E \rightarrow E + n \mid E \times n \mid n$ For a sentence $n + n \times n$, the handles in the right-sentential form of the reduction are: $n, E + n$ and $E + n \times n$ $n, E + n$ and $E + E \times n$ $n, n + n$ and $n + n \times n$ $n, E + n$ and $E \times n$

asked Sep 22, 2014 in Compiler Design Kathleen 7.5k views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

GO Book for GATECSE 2022

Subjects

Network Sites

Recent questions tagged gate2005-cse

Log In

Register

GO Book for GATECSE 2022

Recent Posts

Subjects

Recent Blog Comments

Network Sites

Recent questions tagged gate2005-cse