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Recent questions tagged go-digital-logic-1

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1
GATE Overflow | Digital Logic | Test 1 | Question: 30
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature? cross coupling gate impedance low input voltages asynchronous operation
Latches constructed with NOR and NAND gates tend to remain in the latched condition due to which configuration feature?cross couplinggate impedancelow input voltagesasync...
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GATE Overflow | Digital Logic | Test 1 | Question: 29
The minimum number of gates required to implement the Boolean function $(AB+C)$ if we have to use only 2-input NOR gate?
The minimum number of gates required to implement the Boolean function $(AB+C)$ if we have to use only 2-input NOR gate?
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GATE Overflow | Digital Logic | Test 1 | Question: 28
Zero has only one representation in Sign magnitude 1's complement 2's complement Both 1's complement and 2's complement
Zero has only one representation inSign magnitude1's complement2's complementBoth 1's complement and 2's complement
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GATE Overflow | Digital Logic | Test 1 | Question: 26
Which of the following operations is commutative but not associative ? AND OR NAND EXOR
Which of the following operations is commutative but not associative ?ANDORNANDEXOR
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GATE Overflow | Digital Logic | Test 1 | Question: 24
What is minimum number of NAND gates required to implement a 2 input EX-OR gate without using any other logic gates?
What is minimum number of NAND gates required to implement a 2 input EX-OR gate without using any other logic gates?
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GATE Overflow | Digital Logic | Test 1 | Question: 21
What is the final value stored in the linear feedback shift register if the input is 101101? $0110$ $1011$ $1101$ $1111$
What is the final value stored in the linear feedback shift register if the input is 101101?$0110$$1011$$1101$$1111$
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GATE Overflow | Digital Logic | Test 1 | Question: 20
The minimum number of $T$ –gates required to implement the following function is $F(w,x,y,z) = \sum m (0,1,2,4,7,8,9,10,12,15) $
The minimum number of $T$ –gates required to implement the following function is$$F(w,x,y,z) = \sum m (0,1,2,4,7,8,9,10,12,15) $$
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GATE Overflow | Digital Logic | Test 1 | Question: 19
The Min-term expansion of $F(P,Q,R)= PQ+Q\bar R+P\bar R$ is $m_2 + m_4 + m_6 + m_7$ $ m_0 + m_1 + m_6 + m_7$ $m_0 + m_1 + m_3 + m_5$ $m_2 + m_3 + m_4 + m_5$
The Min-term expansion of $F(P,Q,R)= PQ+Q\bar R+P\bar R$ is$m_2 + m_4 + m_6 + m_7$$ m_0 + m_1 + m_6 + m_7$$m_0 + m_1 + m_3 + m_5$$m_2 + m_3 + m_4 + m_5$
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GATE Overflow | Digital Logic | Test 1 | Question: 18
The conversion $(E7C.B)_{16}$ to octal is equal to $( 8483.9)_8$ $(6894.4)_8$ $(8124.5)_8$ $(7174.54)_8$
The conversion $(E7C.B)_{16}$ to octal is equal to$( 8483.9)_8$$(6894.4)_8$$(8124.5)_8$$(7174.54)_8$
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GATE Overflow | Digital Logic | Test 1 | Question: 17
Which of the following is equivalent expression to $A \oplus B \oplus C$ : $(A+B+C)(\bar A+\bar B+\bar C ) $ $( A+B+C) (\bar A +\bar B +C)$ $ABC + \bar A(B \oplus C ) + \bar B (A \oplus C )$ None
Which of the following is equivalent expression to $A \oplus B \oplus C$ :$(A+B+C)(\bar A+\bar B+\bar C ) $$( A+B+C) (\bar A +\bar B +C)$$ABC + \bar A(B \oplus C ) + \bar...
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GATE Overflow | Digital Logic | Test 1 | Question: 16
The output of a gated S-R flip-flop changes only if the: flip-flop is set control input data has changed flip-flop is reset input data has no change
The output of a gated S-R flip-flop changes only if the:flip-flop is setcontrol input data has changedflip-flop is resetinput data has no change
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GATE Overflow | Digital Logic | Test 1 | Question: 15
The addition of 4 bits two complement binary numbers $1101$ and $0100$ results in 0001 and an overflow 1001 and no overflow 0001 and no overflow 1001 and an overflow
The addition of 4 bits two complement binary numbers $1101$ and $0100$ results in0001 and an overflow1001 and no overflow0001 and no overflow1001 and an overflow
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GATE Overflow | Digital Logic | Test 1 | Question: 10
Total number of full and half-adders require to add 32 bit numbers is 16 half adders , 16 full adders 1 half-adders , 31 full-adders 32 half-adders, 0 full-adders 16 half-adders, 31 full-adders
Total number of full and half-adders require to add 32 bit numbers is16 half adders , 16 full adders1 half-adders , 31 full-adders32 half-adders, 0 full-adders16 half-add...
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3 answers
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GATE Overflow | Digital Logic | Test 1 | Question: 9
Reduce this Boolean Expression to one literal $\bar W X( \bar Z +\bar YZ ) + X( W+\bar WYZ)$ $W$ $Z$ $X$ $Y$
Reduce this Boolean Expression to one literal$$\bar W X( \bar Z +\bar YZ ) + X( W+\bar WYZ)$$$W$$Z$$X$$Y$
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1 votes
3 answers
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GATE Overflow | Digital Logic | Test 1 | Question: 6
The minimum number of Flip-Flops required to construct a binary Modulo $n$ counter is ________ $n$ $n-1$ $2^n – 1$ $\lceil \log_2 n \rceil$
The minimum number of Flip-Flops required to construct a binary Modulo $n$ counter is ________$n$$n-1$$2^n – 1$$\lceil \log_2 n \rceil$
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2 answers
26
GATE Overflow | Digital Logic | Test 1 | Question: 5
Which function does not implement the Karnaugh Map given below? wz 00 01 11 10 xy 00 0 x 0 0 01 0 x 1 1 11 1 1 1 1 10 0 x 0 0 $(w+x)y$ $xy + yw$ $(w+x) (\bar w + y) (\bar x + y)$ All of the above implement the given Karnaugh Map
Which function does not implement the Karnaugh Map given below?wz00011110xy000x00010x11111111100x00$(w+x)y$$xy + yw$$(w+x) (\bar w + y) (\bar x + y)$All of the above impl...
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2 votes
1 answer
28
GATE Overflow | Digital Logic | Test 1 | Question: 3
The advantage of Synchronous Sequential circuits over Asynchronous Sequential circuits is : Faster operation Easy to avoid problems due to Hazards Lower hardware requirement None
The advantage of Synchronous Sequential circuits over Asynchronous Sequential circuits is :Faster operationEasy to avoid problems due to HazardsLower hardware requirement...
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