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Recent questions tagged input-output
1
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61
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 7 (Page No. 430)
One mode that some DMA controllers use is to have the device controller send the word to the DMA controller, which then issues a second bus request to write to memory. How can this mode be used to perform ... Discuss any advantage or disadvantage of using this method instead of using the CPU to perform memory to memory copy.
One mode that some DMA controllers use is to have the device controller send the word to the DMA controller, which then issues a second bus request to write to memory. Ho...
admin
606
views
admin
asked
Oct 28, 2019
Operating System
tanenbaum
operating-system
input-output
dma
descriptive
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3
votes
1
answer
62
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 6 (Page No. 429 - 430)
Suppose that a system uses DMA for data transfer from disk controller to main memory. Further assume that it takes $t_{1}\: nsec$ on average to acquire the bus and $t_{2}\:nsec$ to transfer one word ... acquiring the bus to send one word and acknowledging a transfer also requires acquiring the bus to send one word.
Suppose that a system uses DMA for data transfer from disk controller to main memory. Further assume that it takes $t_{1}\: nsec$ on average to acquire the bus and $t_{2}...
admin
1.1k
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admin
asked
Oct 28, 2019
Operating System
tanenbaum
operating-system
input-output
dma
descriptive
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4
votes
2
answers
63
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 5 (Page No. 429)
A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have to be to avoid being a bottleneck?
A DMA controller has five channels. The controller is capable of requesting a $32$-bit word every $40\: nsec.$ A response takes equally long. How fast does the bus have t...
admin
2.2k
views
admin
asked
Oct 28, 2019
Operating System
tanenbaum
operating-system
input-output
dma
descriptive
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–
0
votes
0
answers
64
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 4 (Page No. 429)
Explain the tradeoffs between precise and imprecise interrupts on a superscalar machine.
Explain the tradeoffs between precise and imprecise interrupts on a superscalar machine.
admin
361
views
admin
asked
Oct 28, 2019
Operating System
tanenbaum
operating-system
input-output
interrupts
descriptive
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–
0
votes
0
answers
65
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 3 (Page No. 429)
Figure $5-3(b)$ shows one way of having memory-mapped I/O even in the presence of separate buses for memory and I/O devices, namely, to first try the memory bus and if that fails try the I/O bus. A clever computer ... idea: try both in parallel, to speed up the process of accessing I/O devices. What do you think of this idea?
Figure $5-3(b)$ shows one way of having memory-mapped I/O even in the presence of separate buses for memory and I/O devices, namely, to first try the memory bus and if th...
admin
402
views
admin
asked
Oct 28, 2019
Operating System
tanenbaum
operating-system
input-output
memory-mapped
descriptive
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0
votes
0
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66
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 2 (Page No. 429)
Given the speeds listed in Fig. $5-1,$ is it possible to scan documents from a scanner and transmit them over an $802.11g$ network at full speed? Defend your answer.
Given the speeds listed in Fig. $5-1,$ is it possible to scan documents from a scanner and transmit them over an $802.11g$ network at full speed? Defend your answer.
admin
194
views
admin
asked
Oct 28, 2019
Operating System
tanenbaum
operating-system
input-output
descriptive
+
–
1
votes
0
answers
67
Andrew S. Tanenbaum (OS) Edition 4 Exercise 5 Question 1 (Page No. 429)
Advances in chip technology have made it possible to put an entire controller, including all the bus access logic, on an inexpensive chip. How does that affect the model of Fig. $1-6?$
Advances in chip technology have made it possible to put an entire controller, including all the bus access logic, on an inexpensive chip. How does that affect the model ...
admin
385
views
admin
asked
Oct 28, 2019
Operating System
tanenbaum
operating-system
input-output
descriptive
+
–
1
votes
1
answer
68
self doubt
Difference between both synchronous and asynchronous I/O on the based of ISR . Means when they are going to invoked during i/o completion ( i.e. before, after ?????? )
Difference between both synchronous and asynchronous I/O on the based of ISR . Means when they are going to invoked during i/o completion ( i.e. before, after ?????? )
Deepanshu
306
views
Deepanshu
asked
Nov 3, 2018
CO and Architecture
co-and-architecture
input-output
self-doubt
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1
votes
0
answers
69
GATE CSE 1987 | Question: 5a
Eight $7$-segment LED displays and a keyboard consisting of $28$ keys are to be interfaced to a microprocessor based system. Give the block diagram of the interface circuit using minimum number of port lines from any programmable I/O chip. Use any other IC chip if necessary.
Eight $7$-segment LED displays and a keyboard consisting of $28$ keys are to be interfaced to a microprocessor based system. Give the block diagram of the interface circu...
makhdoom ghaya
401
views
makhdoom ghaya
asked
Nov 11, 2016
CO and Architecture
gate1987
co-and-architecture
input-output
descriptive
out-of-gate-syllabus
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