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31
ISRO 2007-ECE Memory
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to design the memory system is a) 2 b) 4 c) 8 d) 16
A memory system of size 16K bytes is required to be designed using memory chips, which have 12 address lines and 4 data lines each. The number of such chips required to d...
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1 answer
32
ISRO 2007- ECE combinational logic circuit
The combinational logic circuit shown in the given figure has an output Q which is a) ABC b) A+B+C c)A ⊕ B ⊕ C d) A. B+C
The combinational logic circuit shown in the given figure has an output Q which isa) ABCb) A+B+Cc)A ⊕ B ⊕ Cd) A. B+C
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34
ISRO 2007-ECE Counters
A 4-bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required for change of state will be a) 25 ns b) 50 ns c) 75 ns d) 100 ns
A 4-bit synchronous counter uses flip-flops with propagation delay time of 25 ns each. The maximum possible time required for change of state will bea) 25 nsb) 50 nsc) 75...
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35
ISRO 2007-ECE Up counter
A 4-bit presetable UP counter has preset input 0101. The preset operation takes place as soon as the counter reaches 1111. The modulus of the counter is a) 5 b) 10 c) 11 d) 15
A 4-bit presetable UP counter has preset input 0101. The preset operation takes place as soon as the counter reaches 1111. The modulus of the counter isa) 5b) 10c) 11d) 1...
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36
ISRO 2007-ECE : Binary Codes
The logic circuit given below converts a binary code Y1 Y2 Y3 into a) Excess -3 code b) Gray code c) BCD code d) Hamming code
The logic circuit given below converts a binary code Y1 Y2 Y3 intoa) Excess -3 codeb) Gray codec) BCD coded) Hamming code
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37
ISRO 2007-ECE Boolean Dual
For the identity $AB + A' C + BC = AB + A' C$, the dual form is $(A+B) (A'+C)(B+C)= (A+B)(A'+C)$ $(A'+ B') ( A' + C') (B'+C')= (A'+ B') (A +C')$ $(A+B) (A'+C) (B+C) = (A'+ B') (A+ C')$ $A'B'+AC'+ B'C'= A'B'+AC'$
For the identity $AB + A' C + BC = AB + A' C$, the dual form is$(A+B) (A'+C)(B+C)= (A+B)(A'+C)$$(A'+ B') ( A' + C') (B'+C')= (A'+ B') (A +C')$$(A+B) (A'+C) (B+C) = (A'+ B...
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38
ISRO 2007- ECE Combinational circuit
The Boolean expression for the output of the logic circuit shown in the figure is $Y=AB+ A'B'+C$ $Y= AB+A'B'+ C'$ $Y=A B'+ A'B+C$ $Y=AB+ A'B+ C'$
The Boolean expression for the output of the logic circuit shown in the figure is$Y=AB+ A'B'+C$$Y= AB+A'B'+ C'$$Y=A B'+ A'B+C$$Y=AB+ A'B+ C'$
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39
ISRO 2007-ECE Conversion to binaty number
Which of the following binary number is equal to octal number 66.3 a) 101101.100 b) 1101111.111 c) 111111.1111 d) 110110.011
Which of the following binary number is equal to octal number 66.3 a) 101101.100b) 1101111.111c) 111111.1111d) 110110.011
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40
ISRO 2007- ECE Digital logic
The circuit is a a) Monostable MV b) Astable MV c) Adder d) SR FF
The circuit is aa) Monostable MVb) Astable MVc) Adderd) SR FF
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42
ISRO 2007-ECE Half Adder Circuit
A half adder can be constructed using two $2$-input logic gates. One of them is an $\text{AND}$-gate, the other is $\text{OR}$ $\text{NAND}$ $\text{NOR}$ $\text{EX-OR}$
A half adder can be constructed using two $2$-input logic gates. One of them is an $\text{AND}$-gate, the other is$\text{OR}$$\text{NAND}$$\text{NOR}$$\text{EX-OR}$
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43
ISRO 2008- ECE adjoint Matrix
The matrix is its own adjoint. The value of x will be (a) 5 (b) 3 (c) -3 (d) -5
The matrix is its own adjoint. The value of x will be(a) 5 (b) 3 (c) -3 (d) -5
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44
ISRO 2008- ECE GOTO statement
The "go to statement" causes control to go to (a) An operator (b) A label (c) A variable (d) A function
The "go to statement" causes control to go to(a) An operator(b) A label(c) A variable(d) A function
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45
ISRO 2008-ECE exit() function
The library function exit ( ) causes as exit from (a) the loop in which it occurs (b) the block is which it occurs (c) the functions in which it occurs (d) the progam in which it occurs
The library function exit ( ) causes as exit from (a) the loop in which it occurs(b) the block is which it occurs(c) the functions in which it occurs(d) the progam in whi...
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46
ISRO 2008-ECE programming
A program having features such as data abstraction, encapsulation and data hiding, polymorphism inheritance is called (a) Structured program (b) Object oriented program (c) Open source program (d) Real time program
A program having features such as data abstraction, encapsulation and data hiding, polymorphism inheritance is called(a) Structured program(b) Object oriented program(c) ...
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48
ISRO 2008-ECE Integration
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49
ISRO 2008-ECE Moore model for squntial circuits
Which of the following represents the Moore model for sequential circuits?
Which of the following represents the Moore model for sequential circuits?
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50
ISRO 2008-ECE Computer architecture
Digital signal processors use a computer architecture derived from (a) Harvard Architecture (b) Von-Neumann Architecture (c) Cray Architecture (d) None of the above
Digital signal processors use a computer architecture derived from(a) Harvard Architecture(b) Von-Neumann Architecture(c) Cray Architecture(d) None of the above
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52
ISRO 2008- ECE PROM
A programmable device (PROM) is (a) programmable OR and fixed AND array (b) programmable AND and fixed OR array (c) programmable AND and programmable OR array (d) none
A programmable device (PROM) is(a) programmable OR and fixed AND array(b) programmable AND and fixed OR array(c) programmable AND and programmable OR array(d) none
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53
ISRO 2008-ECE - Ripple counter
In a ripple counter how many changes in state happen when count changes from 7 to 8? (a)$1$ (b)$2$ (c)$3$ (d)$4$
In a ripple counter how many changes in state happen when count changes from 7 to 8?(a)$1$(b)$2$(c)$3$(d)$4$
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2 answers
54
ISRO 2008- ECE minimum number of NAND Gates
Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF is (a) 4 (b) 5 (c) 6 (d) 7
Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF is(a) 4(b) 5(c) 6(d) 7
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55
ISRO 2008-ECE A/D Converter
The number of comparators required in an 8-bit flash-type A/D converter is (a) 256 (b) 255 (c) 9 (d) 8
The number of comparators required in an 8-bit flash-type A/D converter is(a) 256(b) 255(c) 9(d) 8
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1 votes
2 answers
56
ISRO 2008-ECE Pipeline
Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is (a) $2N$ (b) $N^ 2$ (c) $N$ (d) $N!$
Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is(a) $2N$(b) $N^ 2$(c) $N$(d) $N!$
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57
ISRO 2008-ECE RS 232 interface
RS-232 interface (a) Uses only positive voltage (b) Cannot transmit signals over long distance . (c) Uses only negative voltage (d) A logic high uses positive voltage
RS-232 interface(a) Uses only positive voltage(b) Cannot transmit signals over long distance .(c) Uses only negative voltage(d) A logic high uses positive voltage
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59
ISRO 2008-ECE Maths / Vectors
The value of c which makes the angle 45° between a = i + cj and b = i+ j is a) 1 b) 1/ √ 2 c) -1/ √ 2 d) 0
The value of c which makes the angle 45° between a = i + cj and b = i+ j isa) 1b) 1/ √ 2c) -1/ √ 2d) 0
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60
ISRO 2008- ECE Flip flop counter
A counter is designed with six stages of flip flops. Determine the output frequency at the last (sixth) stage, when input frequency is $1$ $MHz$. $1$ $MHz$ $166$ $KHz$ $15.625$ $KHz$ $0$
A counter is designed with six stages of flip flops. Determine the output frequency at the last (sixth) stage, when input frequency is $1$ $MHz$.$1$ $MHz$$166$ $KHz$$15.6...
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