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Recent questions tagged machine-instructions

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Unacademy Practice Question
Consider a 4 way set associative cache of size 16 KB organized into 4 words block. Cache memory is designed with the write back protocol having the miss ratio of read and write operations as 30% and 40% respectively. The tine taken by ... 50% read requests and 50% write requests. What is the average memory access time considering both read and write operations ?

Swarnava Bose asked in CO and Architecture Feb 1

by Swarnava Bose

191 views

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1 answer

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Practice Question Unacademy - Vishvadeep Gothi
Consider a system which supports 2-address, 1-address and 0-address instructions. The system has 'i' bits instructions and 'a' bits addresses. If there are 'x' 2-address instructions and 'y' 1-address instructions then which of the following is the maximum number of 0-address instructions ... $2 ^ i - 2 ^ a * x - y * 2 ^ a$

bsreevidya asked in CO and Architecture Jan 22

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1 vote

3 answers

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CO and Arcitecture | RISC | Instruction pipelining
MSQ Which among the following statements is/are TRUE for a pipelined RISC computer. PC is usually incremented during Instruction Cycle (IF,ID) PC may be incremented during Execution Cycle (EX,MA,WB) Filling the Accumulator ... during the Instruction Cycle (IF,ID) All non-register memory fetching operations are done in Load instructions only.

Souvik33 asked in CO and Architecture Dec 16, 2022

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SelfDoubt
During the instruction fetch does the program counter increment in the same clock cycle or it take next clock cycle

someshawasthi asked in CO and Architecture Oct 27, 2022

by someshawasthi

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pipelining with branch instructions
ADD R1,R2,R3 SUB R2,R1,R7 BNEQZ R5,L1 MUL R8,R9,R3 DIV R6,R8,R7 L1:- LOAD R4, 2(R6) SUB R10,R4,R11 for the above sequence of instructions draw time and space diagram to find out total number of clock cycles required to complete execution without operand forwarding and if branch is not taken

anas_2908 asked in CO and Architecture Oct 21, 2022

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Best Open Video Playlist for Machine Instructions Topic | CO & A
Please list out the best free available video playlist for Machine Instructions from CO & A as an answer here (only one playlist per answer). We'll then select the best playlist and add to GO classroom video lists. ... but standard ones are more likely to be selected as best. For the full list of selected videos please see here

makhdoom ghaya asked in Study Resources Aug 16, 2022

by makhdoom ghaya

98 views

1 vote

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4 Address Instruction
Where are 4 Address Instructions are used and how?

prashastinama asked in CO and Architecture Oct 3, 2021

by prashastinama

266 views

3 votes

1 answer

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How carry and zero flag bits are modified after CMP instruction is executed?
The instruction format is CMP R1, R2. How will the carry and zero flags we be modified after above instruction is executed? Case 1: R1< R2 Carry Flag = 1 Zero Flag = 0 R1= R2 Carry Flag = 0 Zero Flag = 1 R1> R2 ... 0 Zero Flag = 1 R1> R2 Carry Flag = 1 Zero Flag = 0 Which one of the above two cases is correct?

jaswanth431 asked in CO and Architecture Sep 5, 2021

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GATE CSE 2021 Set 1 | Question: 55
Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the memory location $\text{X}.$ ... . Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

5.4k views

1 vote

2 answers

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UGC NET CSE | October 2020 | Part 2 | Question: 75
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$

go_editor asked in CO and Architecture Nov 20, 2020

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NIELIT 2016 MAR Scientist C - Section C: 45
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control

Lakshman Patel RJIT asked in CO and Architecture Apr 2, 2020

by Lakshman Patel RJIT

1.4k views

3 votes

1 answer

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NIELIT 2017 OCT Scientific Assistant A (IT) - Section C: 8
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

1.2k views

1 vote

2 answers

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NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 35
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

1.2k views

4 votes

1 answer

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NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 3
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

525 views

1 vote

2 answers

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NIELIT 2016 DEC Scientist B (IT) - Section B: 39
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data

Lakshman Patel RJIT asked in CO and Architecture Mar 31, 2020

by Lakshman Patel RJIT

590 views

0 votes

2 answers

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UGC NET CSE | January 2017 | Part 2 | Question: 32
Consider the following assembly language instructions: mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0 What is the value in $ax$ register after execution of above instructions? $0270H$ $0170H$ $01E0H$ $0370H$

go_editor asked in CO and Architecture Mar 24, 2020

2.6k views

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3 answers

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UGC NET CSE | January 2017 | Part 2 | Question: 34
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and sign flag $(SF)$ after executing $'SUB AL, BL'$ ... $AL =F1H; \: CF = 1; \: SF= 1$ $AL =1FH; \: CF=1; \:SF=1$

go_editor asked in CO and Architecture Mar 24, 2020

2.2k views

21 votes

6 answers

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GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.

Arjun asked in CO and Architecture Feb 12, 2020

by Arjun

23.0k views

5 votes

3 answers

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ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ ... by how many $\text{MOV}$ instructions? $\text{Case 2,2}$ $\text{Case 2,3}$ $\text{Case 1,2}$ $\text{Case 1,3}$

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

2.5k views

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 32 (Page No. 176)
Show how counting semaphores (i.e., semaphores that can hold an arbitrary value) can be implemented using only binary semaphores and ordinary machine instructions.

Lakshman Patel RJIT asked in Operating System Oct 25, 2019

by Lakshman Patel RJIT

255 views

1 vote

4 answers

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Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 14 (Page No. 82)
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?

Lakshman Patel RJIT asked in CO and Architecture Oct 23, 2019

by Lakshman Patel RJIT

1.3k views

2 votes

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MadeEasy Test Series 2019: CO & Architecture - Machine Instruction
Q.A stack based CPU executes the instruction.Memory location 500 contains 0x88 and memory location 700 contains 0x37.The stack pointer is at 0x003F. The instructions are as follows: I1:PUSH 500 I2:PUSH 700 I3:ADD ... after execution instructions c)Memory location 600 contains 0xBF after execution instructions d)Both (a) and (c)

Badayayash asked in CO and Architecture Jan 20, 2019

1.2k views

4 votes

3 answers

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Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?

Rishav Chetan asked in CO and Architecture Jan 19, 2019

by Rishav Chetan

741 views

1 vote

1 answer

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Calculate number of times Zero Flag is Reset
I am getting 37.

Shubhanshu asked in CO and Architecture Jan 8, 2019

919 views

1 vote

2 answers

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Word Addressable (GATE 2004)

Na462 asked in CO and Architecture Jan 5, 2019

by Na462

1.3k views

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Recent questions tagged machine-instructions