Recent questions tagged machine-instructions

Recent questions tagged machine-instructions

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1

4 Address Instruction
Where are 4 Address Instructions are used and how?

prashastinama asked in CO and Architecture Oct 3, 2021

by prashastinama

95 views

1 vote

1 answer

2

How carry and zero flag bits are modified after CMP instruction is executed?
The instruction format is CMP R1, R2. How will the carry and zero flags we be modified after above instruction is executed? Case 1: R1< R2 Carry Flag = 1 Zero Flag = 0 R1= R2 Carry Flag = 0 Zero Flag = 1 R1> R2 ... 0 Zero Flag = 1 R1> R2 Carry Flag = 1 Zero Flag = 0 Which one of the above two cases is correct?

jaswanth431 asked in CO and Architecture Sep 5, 2021

154 views

4 votes

3 answers

3

GATE CSE 2021 Set 1 | Question: 55
Consider the following instruction sequence where registers $\text{R1}, \text{R2}$ and $\text{R3}$ are general purpose and $\text{MEMORY[X]}$ denotes the content at the memory location $\text{X}.$ ... . Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________

Arjun asked in CO and Architecture Feb 18, 2021

by Arjun

2.5k views

0 votes

2 answers

4

UGCNET-Oct2020-II: 75
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$

jothee asked in CO and Architecture Nov 20, 2020

by jothee

621 views

0 votes

2 answers

5

NIELIT 2016 MAR Scientist C - Section C: 45
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control

Lakshman Patel RJIT asked in CO and Architecture Apr 2, 2020

by Lakshman Patel RJIT

978 views

3 votes

1 answer

6

NIELIT 2017 OCT Scientific Assistant A (IT) - Section C: 8
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

910 views

1 vote

2 answers

7

NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 35
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

676 views

4 votes

1 answer

8

NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 3
Match list $I$ with List $II$ ... iii, D-iv A-iii, B-ii, C-iv, D-i A-ii, B-iii, C-i, D-iv A-i, B-iv, C-ii, D-iii

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

395 views

1 vote

2 answers

9

NIELIT 2016 DEC Scientist B (IT) - Section B: 39
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data

Lakshman Patel RJIT asked in CO and Architecture Mar 31, 2020

by Lakshman Patel RJIT

470 views

0 votes

1 answer

10

UGCNET-Jan2017-II: 32
Consider the following assembly language instructions: mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0 What is the value in $ax$ register after execution of above instructions? $0270H$ $0170H$ $01E0H$ $0370H$

jothee asked in CO and Architecture Mar 24, 2020

by jothee

1.6k views

0 votes

1 answer

11

UGCNET-Jan2017-II: 34
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and sign flag $(SF)$ after executing $'SUB AL, BL'$ assembly language instruction, are $AL=0FH; \: CF=1; \: SF= 1$ $AL = F0H; \: CF = 0; \: SF = 0$ $AL =F1H; \: CF = 1; \: SF= 1$ $AL =1FH; \: CF=1; \:SF=1$

jothee asked in CO and Architecture Mar 24, 2020

by jothee

1.3k views

17 votes

6 answers

12

GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.

Arjun asked in CO and Architecture Feb 12, 2020

by Arjun

18.3k views

3 votes

3 answers

13

ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ ... by how many $\text{MOV}$ instructions? $\text{Case 2,2}$ $\text{Case 2,3}$ $\text{Case 1,2}$ $\text{Case 1,3}$

Satbir asked in CO and Architecture Jan 13, 2020

by Satbir

1.6k views

0 votes

0 answers

14

Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 32 (Page No. 176)
Show how counting semaphores (i.e., semaphores that can hold an arbitrary value) can be implemented using only binary semaphores and ordinary machine instructions.

Lakshman Patel RJIT asked in Operating System Oct 25, 2019

by Lakshman Patel RJIT

167 views

0 votes

4 answers

15

Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 14 (Page No. 82)
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?

Lakshman Patel RJIT asked in CO and Architecture Oct 23, 2019

by Lakshman Patel RJIT

813 views

0 votes

1 answer

16

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

learner_geek asked in CO and Architecture Feb 1, 2019

by learner_geek

2k views

2 votes

0 answers

17

MadeEasy Test Series 2019: CO & Architecture - Machine Instruction
Q.A stack based CPU executes the instruction.Memory location 500 contains 0x88 and memory location 700 contains 0x37.The stack pointer is at 0x003F. The instructions are as follows: I1:PUSH 500 I2:PUSH 700 I3:ADD ... after execution instructions c)Memory location 600 contains 0xBF after execution instructions d)Both (a) and (c)

Badayayash asked in CO and Architecture Jan 20, 2019

1k views

3 votes

3 answers

18

Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?

Rishav Chetan asked in CO and Architecture Jan 19, 2019

by Rishav Chetan

506 views

0 votes

0 answers

19

MadeEasy Full Length Test 2019: CO & Architecture - Machine Instructions
A stack based CPU executes the instruction. Memory location 500 contain 0x88 and memory location 700 contains 0x37. The stack pointer is at 0x003F. The instructions are as follows: $I_1 -$ PUSH 500 $I_2 -$ PUSH 700 $I_ 3-$ ... in to use Ginger Limited mode $I_2: PUSH300$ Log in to use Ginger Limited mode $I_2: $PUSH300

shreyansh jain asked in CO and Architecture Jan 16, 2019

by shreyansh jain

389 views

1 vote

1 answer

20

Calculate number of times Zero Flag is Reset
I am getting 37.

Shubhanshu asked in CO and Architecture Jan 8, 2019

618 views

1 vote

2 answers

21

Word Addressable (GATE 2004)

Na462 asked in CO and Architecture Jan 5, 2019

by Na462

991 views

0 votes

2 answers

22

AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.

shaz asked in CO and Architecture Dec 13, 2018

by shaz

417 views

2 votes

1 answer

23

RISC processor doubt
is the CPI of RISC processor always 1?

aditi19 asked in CO and Architecture Dec 10, 2018

871 views

0 votes

0 answers

24

Zeal Test Series 2019: CO & Architecture - Machine Instruction
i am getting D) answer is c)

Prince Sindhiya asked in CO and Architecture Dec 8, 2018

by Prince Sindhiya

293 views

3 votes

2 answers

25

CO & architecture
The arithmetic expression $: (a + b) \ast c - d / e \ast \ast f$ is to be evaluated on a two-address machine, where each operands, the number of registers required to evaluate this expression is ______. The number of memory access of operand is __________.

Satbir asked in CO and Architecture Nov 26, 2018

by Satbir

938 views

0 votes

0 answers

26

adressing modes
For Given machine instructions LW R4 #400 L1:LW R1, 0,(R4) LW R2 400(R4) ADDI R3, R1, R2 SW R3, 0(R4) SUB R4, R4, #4 BNZ R4, L1 on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?

rishabhdevsingh1 asked in CO and Architecture Nov 10, 2018

by rishabhdevsingh1

352 views

0 votes

1 answer

27

adressing modes
Given 2 machine instructions, LW R4 #400 LW R1, 0,(R4) IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory location operand..I want to clarify weather value stored in register is same as adress that register points.

rishabhdevsingh1 asked in CO and Architecture Nov 9, 2018

by rishabhdevsingh1

497 views

1 vote

1 answer

28

Computer Organization
Consider the following program segment used to execute on a hypothetical processor. Consider all the registers are of 16 bit size I1 MOV CX,0005 ; CX ← 0005 I2 MOV BX,OFF7H ; BX ← OFF7H I3 MOV AX,OBCAH ; AX ← OBCAH I4 OR BX,AX ; BX ← ... 4 cycles and transfer of control operations takes 2 cycles to execute. How much time is required to execute the program on a above CPU?

Sumit Singh Chauhan asked in CO and Architecture Sep 2, 2018

by Sumit Singh Chauhan

1.3k views

4 votes

1 answer

29

Computer Organization
A computer has 256 K word memory. The instruction format has 4 fields i.e., Opcode, register field to represent one of the 60 processor registers, mode field represent one of 7 addressing modes and memory address field. How many instructions the system supports when a 32- bit instruction is placed in the one memory cell.

Sumit Singh Chauhan asked in CO and Architecture Sep 2, 2018

by Sumit Singh Chauhan

5.9k views

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