Recent questions tagged machine-instructions

+2 votes

1 answer

1

ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $ADD, SUB$ and $MOV$. Consider $2$ ... is better in terms of memory accesses and by how many $MOV$ instructions ? Case $2,2$ Case $2,3$ Case $1,2$ Case $1,3$

asked Jan 13 in CO and Architecture by Satbir Boss (23.9k points) | 191 views

0 votes

0 answers

2

Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 32 (Page No. 176)
Show how counting semaphores (i.e., semaphores that can hold an arbitrary value) can be implemented using only binary semaphores and ordinary machine instructions.

asked Oct 25, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.9k points) | 17 views

0 votes

1 answer

3

Andrew S. Tanenbaum (OS) Edition 4 Exercise 1 Question 14 (Page No. 82)
A computer has a pipeline with four stages. Each stage takes the same time to do its work, namely, $1$ nsec. How many instructions per second can this machine execute?

asked Oct 23, 2019 in Operating System by Lakshman Patel RJIT Veteran (58.9k points) | 39 views

0 votes

1 answer

4

computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.

asked Feb 1, 2019 in CO and Architecture by learner_geek Active (3.3k points) | 384 views

+1 vote

0 answers

5

MadeEasy Test Series 2019: CO & Architecture - Machine Instruction
Q.A stack based CPU executes the instruction.Memory location 500 contains 0x88 and memory location 700 contains 0x37.The stack pointer is at 0x003F. The instructions are as follows: I1:PUSH 500 I2:PUSH 700 I3:ADD ... after execution instructions c)Memory location 600 contains 0xBF after execution instructions d)Both (a) and (c)

asked Jan 20, 2019 in CO and Architecture by Badayayash Junior (989 points) | 234 views

0 votes

2 answers

6

Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?

asked Jan 19, 2019 in CO and Architecture by Rishav Chetan (35 points) | 137 views

0 votes

0 answers

7

MadeEasy Full Length Test 2019: CO & Architecture - Machine Instructions
A stack based CPU executes the instruction. Memory location 500 contain 0x88 and memory location 700 contains 0x37. The stack pointer is at 0x003F. The instructions are as follows: $I_1 -$ PUSH 500 $I_2 -$ PUSH 700 $I_ 3-$ ... in to use Ginger Limited mode $I_2: PUSH300$ Log in to use Ginger Limited mode $I_2: $PUSH300

asked Jan 16, 2019 in CO and Architecture by shreyansh jain Active (2.2k points) | 138 views

+1 vote

0 answers

8

Calculate number of times Zero Flag is Reset
I am getting 37.

asked Jan 8, 2019 in CO and Architecture by Shubhanshu Boss (18.3k points) | 88 views

0 votes

0 answers

9

Word Addressable (GATE 2004)

asked Jan 5, 2019 in CO and Architecture by Na462 Loyal (7k points) | 197 views

0 votes

1 answer

10

AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.

asked Dec 13, 2018 in CO and Architecture by shaz (369 points) | 118 views

0 votes

0 answers

11

RISC processor doubt
is the CPI of RISC processor always 1?

asked Dec 10, 2018 in CO and Architecture by aditi19 Active (5.2k points) | 226 views

0 votes

0 answers

12

Zeal Test Series 2019: CO & Architecture - Machine Instruction
i am getting D) answer is c)

asked Dec 8, 2018 in CO and Architecture by Prince Sindhiya Loyal (5.9k points) | 85 views

0 votes

0 answers

13

adressing modes
For Given machine instructions LW R4 #400 L1:LW R1, 0,(R4) LW R2 400(R4) ADDI R3, R1, R2 SW R3, 0(R4) SUB R4, R4, #4 BNZ R4, L1 on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?

asked Nov 10, 2018 in CO and Architecture by rishabhdevsingh1 (113 points) | 169 views

0 votes

1 answer

14

adressing modes
Given 2 machine instructions, LW R4 #400 LW R1, 0,(R4) IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory location operand..I want to clarify weather value stored in register is same as adress that register points.

asked Nov 9, 2018 in CO and Architecture by rishabhdevsingh1 (113 points) | 115 views

0 votes

0 answers

15

Computer Organization
Consider the following program segment used to execute on a hypothetical processor. Consider all the registers are of 16 bit size I1 MOV CX,0005 ; CX ← 0005 I2 MOV BX,OFF7H ; BX ← OFF7H I3 MOV AX,OBCAH ; AX ← OBCAH I4 OR BX,AX ; BX ← ... 4 cycles and transfer of control operations takes 2 cycles to execute. How much time is required to execute the program on a above CPU?

asked Sep 2, 2018 in CO and Architecture by Sumit Singh Chauhan Active (1.6k points) | 334 views

+3 votes

1 answer

16

Computer Organization
A computer has 256 K word memory. The instruction format has 4 fields i.e., Opcode, register field to represent one of the 60 processor registers, mode field represent one of 7 addressing modes and memory address field. How many instructions the system supports when a 32- bit instruction is placed in the one memory cell.

asked Sep 2, 2018 in CO and Architecture by Sumit Singh Chauhan Active (1.6k points) | 640 views

+3 votes

1 answer

17

Instruction Addressing
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB

asked Jul 31, 2018 in CO and Architecture by Na462 Loyal (7k points) | 361 views

0 votes

1 answer

18

RISC Instruction set
Assume that RISC processor contains 10 global registers, 10 local registers, 6 In registers and 6 Out register. It contain 4 register windows. What is the size of window and register file of the processor? Ans. 32 and 74 Please Explain the Formula and what's the meaning of Window size and register file in RISC Processor ?

asked Jul 27, 2018 in CO and Architecture by Na462 Loyal (7k points) | 464 views

0 votes

3 answers

19

Instruction Execution
Consider the 2 GHz clock frequency processor used execute the following program segment. Assume the 3 clock cycles required for Register to/from memory transfer, 1 clock cycle for ADD with both operands in register, 2 clock cycle MUL with both operands in ... for instruction fetch and decode. What is the total time required to complete the program execution (in ns)? Ans. 18

asked Jul 21, 2018 in CO and Architecture by Na462 Loyal (7k points) | 249 views

0 votes

3 answers

20

Instruction Format
Consider a computer has 64 registers and support 15 different instructions. Each instruction has 4 fields i.e. opcode, source register, destination register and immediate value of 6 bits. If each instruction in byte aligned and 50 instructions are ... answer My question is, in this question what is difference between computer has 15 instruction and memory has 50 instructions?

asked Jun 7, 2018 in CO and Architecture by srestha Veteran (119k points) | 419 views

+34 votes

4 answers

21

GATE2018-51
A processor has $16$ integer registers $(R0, R1, \ldots , R15)$ and $64$ floating point registers $(F0, F1, \ldots , F63).$ It uses a $2- byte$ instruction format. There are four categories of instructions: $Type-1, Type-2, Type-3,$ and $Type-4.$ ... $Type-4$ category consists of $N$ instructions, each with a floating point register operand $(1F).$ The maximum value of $N$ is _____

asked Feb 14, 2018 in CO and Architecture by gatecse Boss (17.5k points) | 7.4k views

+2 votes

1 answer

22

Address after Halt instruction
Consider that the memory is byte addressable with size 16 bits, and the program has been loaded starting from memory location (2000)10. What will be the return address saved in the stack, if an interrupt occurs while the CPU has been halted after executing the HALT instruction? I am getting 2018.

asked Jan 2, 2018 in CO and Architecture by Shubhanshu Boss (18.3k points) | 625 views

+2 votes

1 answer

23

Doubt in CSO
Q1) How processor knows the instruction is one word or more? Q2) Is it possible that opcode in instruction is greater than word size? Q3) What is the format of PSW and how many PSW registers are there?

asked Aug 4, 2017 in CO and Architecture by Shubhanshu Boss (18.3k points) | 423 views

+12 votes

4 answers

24

#ADDRESS INSTRUCTION
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported. A)1 to ... 2-address instructions are already existed.How many one address instructions can be supported ? A)128 B)2 C)256 D)32

asked Jul 24, 2017 in CO and Architecture by junaid ahmad Loyal (8.6k points) | 2.9k views

+1 vote

1 answer

25

Machine Instructions
What is the difference between LOAD/STORE & MOVE instructions?Are they CPU - architecture dependent?

asked Jul 23, 2017 in CO and Architecture by AakS Active (1.9k points) | 536 views

+2 votes

3 answers

26

hamacher

asked Jul 21, 2017 in CO and Architecture by set2018 Loyal (7.8k points) | 332 views

0 votes

1 answer

27

carl Hamacher 6th edition Q.no 5.11
A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows: Branch 20% Load 20% Store 10% Computational instructions 50% Estimate the rate of instruction ... clock cycles. On average, access to the data operands of a Load or Store instruction is completed in 3 clock cycles.

asked Jun 8, 2017 in CO and Architecture by Amit.kumar (483 points) | 311 views

+5 votes

3 answers

28

Implementation of BSA(Branch and save address) instruction
I have a doubt regarding the implementation of BSA instruction. I read that BSA instruction can be implemented as :- T4:- m[AR] <-- PC; AR<--AR+1 T5:- PC<--AR; SC<--0 Here T4 and T5 are 4th and ... to the position where PC is written. So they should happen at different clock cycles right so that they can execute in proper order?

asked Jun 7, 2017 in CO and Architecture by Xylene Active (3.6k points) | 1.2k views

+4 votes

2 answers

29

gatebook mt2 qn-36
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the instructions are loads, 20% are branches, the remaining 50% of instructions are ... dependent instruction, and 75% of branches are predicted correctly. What is the average CPI of this program on this processor?

asked Feb 7, 2017 in CO and Architecture by Purple Active (3k points) | 898 views

+4 votes

1 answer

30

gatebook mt2
A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the sum in Rd */ MUL Rs1, Rs2, Rd /* Multiply Rs1 by Rs2 and put the product in Rd */ An operation ... of clock cycles required for an operation sequence that computes the value of AB + ABC + BC ? (A) 5 (B) 6 (C) 7 (D) 8

asked Feb 7, 2017 in CO and Architecture by Purple Active (3k points) | 652 views

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