Recent questions tagged machine-instructions

+1 vote

1 answer

1

Instruction Addressing
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB

asked Jul 31 in CO & Architecture by Na462 Active (4.5k points) | 42 views

0 votes

1 answer

2

RISC Instruction set
Assume that RISC processor contains 10 global registers, 10 local registers, 6 In registers and 6 Out register. It contain 4 register windows. What is the size of window and register file of the processor? Ans. 32 and 74 Please Explain the Formula and what's the meaning of Window size and register file in RISC Processor ?

asked Jul 27 in CO & Architecture by Na462 Active (4.5k points) | 28 views

0 votes

1 answer

3

Instruction Execution
Consider the 2 GHz clock frequency processor used execute the following program segment. Assume the 3 clock cycles required for Register to/from memory transfer, 1 clock cycle for ADD with both operands in register, 2 clock cycle MUL with both operands in ... for instruction fetch and decode. What is the total time required to complete the program execution (in ns)? Ans. 18

asked Jul 21 in CO & Architecture by Na462 Active (4.5k points) | 30 views

0 votes

1 answer

4

Instruction Format
Consider a computer has 64 registers and support 15 different instructions. Each instruction has 4 fields i.e. opcode, source register, destination register and immediate value of 6 bits. If each instruction in byte aligned and 50 instructions are ... answer My question is, in this question what is difference between computer has 15 instruction and memory has 50 instructions?

asked Jun 7 in CO & Architecture by srestha Veteran (91.6k points) | 84 views

+13 votes

4 answers

5

GATE2018-51
A processor has $16$ integer registers $(R0, R1, \ldots , R15)$ and $64$ floating point registers $(F0, F1, \ldots , F63).$ It uses a $2- byte$ instruction format. There are four categories of instructions: $Type-1, Type-2, Type-3,$ and $Type-4. ... 1F).$ $Type-4$ category consists of $N$ instructions, each with a floating point register operand $(1F).$ The maximum value of $N$ is _____

asked Feb 14 in CO & Architecture by gatecse Boss (18.1k points) | 2.8k views

+3 votes

1 answer

6

Address after Halt instruction
Consider that the memory is byte addressable with size 16 bits, and the program has been loaded starting from memory location (2000)10. What will be the return address saved in the stack, if an interrupt occurs while the CPU has been halted after executing the HALT instruction? I am getting 2018.

asked Jan 2 in CO & Architecture by Shubhanshu Boss (15.1k points) | 225 views

+2 votes

1 answer

7

Doubt in CSO
Q1) How processor knows the instruction is one word or more? Q2) Is it possible that opcode in instruction is greater than word size? Q3) What is the format of PSW and how many PSW registers are there?

asked Aug 4, 2017 in CO & Architecture by Shubhanshu Boss (15.1k points) | 337 views

+8 votes

2 answers

8

#ADDRESS INSTRUCTION
Consider the hypothetical processor is supports both 2 address and one address instructions.It has 128 word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported. A)1 to ... 2-address instructions are already existed.How many one address instructions can be supported ? A)128 B)2 C)256 D)32

asked Jul 24, 2017 in CO & Architecture by junaid ahmad Loyal (9k points) | 1.3k views

+1 vote

1 answer

9

Machine Instructions
What is the difference between LOAD/STORE & MOVE instructions?Are they CPU - architecture dependent?

asked Jul 23, 2017 in CO & Architecture by AakS Active (1.6k points) | 377 views

+2 votes

3 answers

10

hamacher

asked Jul 21, 2017 in CO & Architecture by set2018 Loyal (7.8k points) | 236 views

0 votes

1 answer

11

carl Hamacher 6th edition Q.no 5.11
A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows: Branch 20% Load 20% Store 10% Computational instructions 50% Estimate the rate of instruction ... clock cycles. On average, access to the data operands of a Load or Store instruction is completed in 3 clock cycles.

asked Jun 8, 2017 in CO & Architecture by Amit.kumar (147 points) | 212 views

+3 votes

3 answers

12

Implementation of BSA(Branch and save address) instruction

asked Jun 7, 2017 in CO & Architecture by Xylene Active (3.8k points) | 727 views

+4 votes

2 answers

13

gatebook mt2 qn-36
Consider a simple in-order five-stage pipeline with a two-cycle branch misprediction penalty and a single-cycle load-use delay penalty. For a specific program, 30% of the instructions are loads, 20% are branches, the remaining 50% of instructions are ... dependent instruction, and 75% of branches are predicted correctly. What is the average CPI of this program on this processor?

asked Feb 7, 2017 in CO & Architecture by Purple Active (3.5k points) | 775 views

+4 votes

1 answer

14

gatebook mt2
A certain pipelined RISC machine has 8 general-purpose registers R0, R1, . . . , R7 and supports the following operations. ADD Rs1, Rs2, Rd /* Add Rs1 to Rs2 and put the sum in Rd */ MUL Rs1, Rs2, Rd /* Multiply Rs1 by Rs2 and put the product in Rd */ An operation ... of clock cycles required for an operation sequence that computes the value of AB + ABC + BC ? (A) 5 (B) 6 (C) 7 (D) 8

asked Feb 7, 2017 in CO & Architecture by Purple Active (3.5k points) | 462 views

+8 votes

2 answers

15

Expanding opcode technique
A CPU is designed to have 58 three-address instructions and 25 two-address instructions. The CPU is able to address a maximum of 16 memory locations. The length of machine code is the same for all instructions. If the list of the ... of twoaddress instructions iv) Determine the length of the machine code v) List the machine codes Detailed explanation would be helpful

asked Dec 10, 2016 in CO & Architecture by Prajwal Bhat Boss (11.4k points) | 2.5k views

+7 votes

2 answers

16

ISI2011-CS-6a
Assume a machine has 4 registers (one of which is the accumulator $A$) and the following instruction set. $LOAD$ and $STORE$ are indirect memory operations that load and store, using the address stored in the given register operand. Thus, $LOAD \: R$ ... . Design an instruction encoding scheme that allows each of the above instructions (along with operands) to be encoded in 8 bits.

asked Jun 3, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 458 views

+12 votes

2 answers

17

GATE2003-49
Consider the following assembly language program for a hypothetical processor A, B, and C are 8 bit registers. The meanings of various instructions are shown as comments. MOV B, #0 ; $B \leftarrow 0$ MOV C, #8 ; $C \leftarrow 8$ Z: CMP C, #0 ; compare C with 0 JZ X ; ... as its initial value? RRC A, #1 NOP ; no operation LRC A, #1; left rotate A through carry flag by one bit ADD A, #1

asked Apr 24, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 1.6k views

+24 votes

3 answers

18

GATE2004-64
Consider the following program segment for a hypothetical CPU having three user registers R1, R2 and R3. Instruction Operation Instruction Size (in words) MOV R1, 5000 R1 $\leftarrow$ Memory[5000] 2 MOV R2(R1) R2 $\leftarrow$ Memory[(R1)] 1 ADD R2, R3 ... fetch and decode : 2 clock cycles per word The total number of clock cycles required to execute the program is $29$ $24$ $23$ $20$

asked Apr 24, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 3.3k views

+20 votes

8 answers

19

GATE2005-80
The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for ... \leftarrow M[PC]$; The minimum number of CPU clock cycles needed during the execution cycle of this instruction is: $2$ $3$ $4$ $5$

asked Apr 24, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 3.3k views

+17 votes

3 answers

20

GATE2007-73
Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Instruction Operation Instruction size (no. of words) MOV R1, (3000) R1 $\leftarrow$ m[3000] 2 LOOP: MOV R2, (R3) R2 $\leftarrow$ M[R3] 1 ADD R2, R1 ... during the execution of the instruction “INC R3”, what return address will be pushed on to the stack? 1005 1020 1024 1040

asked Apr 23, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 1.9k views

+15 votes

3 answers

21

GATE2007-72
Consider the following program segment. Here R1, R2 and R3 are the general purpose registers. Instruction Operation Instruction size (no. of words) MOV R1, (3000) R1 $\leftarrow$ m[3000] 2 LOOP: MOV R2, (R3) R2 $\leftarrow$ M[R3] 1 ADD R2, R1 R2 ... . Assume that the memory is word addressable. After the execution of this program, the content of memory location 2010 is: 100 101 102 110

asked Apr 23, 2016 in CO & Architecture by jothee Veteran (99.8k points) | 1.5k views

+28 votes

3 answers

22

GATE2016-2-31
Consider a processor with $64$ registers and an instruction set of size twelve. Each instruction has five distinct fields, namely, opcode, two source register identifiers, one destination register identifier, and twelve-bit immediate value. Each instruction must be ... If a program has $100$ instructions, the amount of memory (in bytes) consumed by the program text is _________.

asked Feb 12, 2016 in CO & Architecture by Akash Kanase Boss (42.6k points) | 4.3k views

+12 votes

2 answers

23

GATE2016-2-10
A processor has $40$ distinct instruction and $24$ general purpose registers. A $32$-bit instruction word has an opcode, two registers operands and an immediate operand. The number of bits available for the immediate operand field is_______.

asked Feb 12, 2016 in CO & Architecture by Akash Kanase Boss (42.6k points) | 2.3k views

+8 votes

4 answers

24

ISRO2015-77
In $X=(M+N \times O)/(P \times Q)$, how many one-address instructions are required to evaluate it? 4 6 8 10

asked Jan 26, 2016 in CO & Architecture by Purple Active (3.5k points) | 2.7k views

+3 votes

0 answers

25

Differencee Between DCR and DCRL Instruction.

asked Nov 29, 2015 in CO & Architecture by kartikey (73 points) | 203 views

+7 votes

3 answers

26

Max number of one address instruction, when two address instruction is given is?

asked Sep 9, 2015 in CO & Architecture by Tehreem (173 points) | 4k views

+2 votes

2 answers

27

consider a hypothetical processor which support both 1 address and zero address instruction.

asked Jun 5, 2015 in CO & Architecture by focus _GATE Boss (20.4k points) | 916 views

+27 votes

2 answers

28

GATE2015-2-42
Consider a processor with byte-addressable memory. Assume that all registers, including program counter (PC) and Program Status Word (PSW), are size of two bytes. A stack in the main memory is implemented from memory location $(0100)_{16}$ and it grows upward. The stack pointer (SP) points ... the value of the stack pointer is: $(016A)_{16}$ $(016C)_{16}$ $(0170)_{16}$ $(0172)_{16}$

asked Feb 13, 2015 in CO & Architecture by jothee Veteran (99.8k points) | 3.1k views

+15 votes

1 answer

29

GATE2004-IT-46
If we use internal data forwarding to speed up the performance of a CPU (R1, R2 and R3 are registers and M[100] is a memory reference), then the sequence of operations R1 → M[100] M[100] → R2 M[100] → R3 can be replaced by R1 → R3 R2 → M[100] M[100] → R2 R1 → R2 R1 → R3 R1 → M[100] R2 → R3 R1 → R2 R1 → R3 R1 → M[100]

asked Nov 2, 2014 in CO & Architecture by Ishrat Jahan Boss (19.1k points) | 1.3k views

+19 votes

3 answers

30

GATE2007-IT-41
Following table indicates the latencies of operations between the instruction producing the result and instruction using the result. Instruction producing the result Instruction using the result Latency ALU Operation ALU operation 2 ALU Operation Store 2 Load ALU Operation ... needed to execute the above code segment assuming each instruction takes one cycle to execute? 7 10 13 14

asked Oct 30, 2014 in CO & Architecture by Ishrat Jahan Boss (19.1k points) | 2.5k views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

Recent questions tagged machine-instructions

Recent Posts

Recent Blog Comments