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Recent questions tagged machine-instructions

0 votes
1 answer
1
GATE CSE 2021 Set 1 | Question: 55
Consider the following instruction sequence where registers $R1, R2$ and $R3$ are general purpose and $\text{MEMORY}[X]$ denotes the content at the memory location $X$ ... that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
Consider the following instruction sequence where registers $R1, R2$ and $R3$ are general purpose and $\text{MEMORY}[X]$ denotes the content at the memory location $X$ ... format. Assume that the memory is byte addressable. After the execution of the program, the content of memory location $3010$ is ____________
asked Feb 18 in CO and Architecture Arjun 372 views
0 votes
2 answers
2
UGCNET-Oct2020-II: 75
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
Arrange the following types of machine in descending order of complexity. SISD MIMD SIMD Choose the correct answer from the options given below: $a,b,c$ $c,b,a$ $b.c.a$ $c,a,b$
asked Nov 20, 2020 in CO and Architecture jothee 194 views
0 votes
1 answer
3
NIELIT 2016 MAR Scientist C - Section C: 45
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control
An instruction used to set the carry flag in a computer can be classified as data transfer process control logical program control
asked Apr 2, 2020 in CO and Architecture Lakshman Patel RJIT 381 views
0 votes
2 answers
5
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 35
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
In a $10$-bit computer instruction format, the size of address field is $3$-bits. The computer uses expanding OP code technique and has $4$ two-address instructions and $16$ one-address instructions. The number of zero address instructions it can support is $256$ $356$ $640$ $756$
asked Apr 1, 2020 in CO and Architecture Lakshman Patel RJIT 386 views
1 vote
2 answers
7
NIELIT 2016 DEC Scientist B (IT) - Section B: 39
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data
MIMD stands for Multiple Instruction Multiple Data Multiple Instruction Memory Data Memory Instruction Multiple data Multiple Information Memory data
asked Mar 31, 2020 in CO and Architecture Lakshman Patel RJIT 317 views
0 votes
1 answer
8
UGCNET-Jan2017-II: 32
Consider the following assembly language instructions: mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0 What is the value in $ax$ register after execution of above instructions? $0270H$ $0170H$ $01E0H$ $0370H$
Consider the following assembly language instructions: mov al, 15 mov ah, 15 xor al, al mov cl, 3 shr ax, cl add al, 90H add ah, 0 What is the value in $ax$ register after execution of above instructions? $0270H$ $0170H$ $01E0H$ $0370H$
asked Mar 24, 2020 in CO and Architecture jothee 848 views
0 votes
1 answer
9
UGCNET-Jan2017-II: 34
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and sign flag $(SF)$ after executing $'SUB AL, BL'$ assembly language instruction, are $AL=0FH; \: CF=1; \: SF= 1$ $AL = F0H; \: CF = 0; \: SF = 0$ $AL =F1H; \: CF = 1; \: SF= 1$ $AL =1FH; \: CF=1; \:SF=1$
The contents of Register $(BL)$ and Register $(AL)$ of $8085$ microprocessor are $49H$ and $3AH$ respectively. The contents of $AL$, the status of carry flag $(CF)$ and sign flag $(SF)$ after executing $'SUB AL, BL'$ assembly language instruction, are $AL=0FH; \: CF=1; \: SF= 1$ $AL = F0H; \: CF = 0; \: SF = 0$ $AL =F1H; \: CF = 1; \: SF= 1$ $AL =1FH; \: CF=1; \:SF=1$
asked Mar 24, 2020 in CO and Architecture jothee 590 views
8 votes
7 answers
10
GATE CSE 2020 | Question: 44
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction ... two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.
A processor has $64$ registers and uses $16$-bit instruction format. It has two types of instructions: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a $4$-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are $8$ distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _______.
asked Feb 12, 2020 in CO and Architecture Arjun 10.4k views
3 votes
3 answers
11
ISRO2020-16
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ ... by how many $\text{MOV}$ instructions? $\text{Case 2,2}$ $\text{Case 2,3}$ $\text{Case 1,2}$ $\text{Case 1,3}$
A computer which issues instructions in order, has only $2$ registers and $3$ opcodes $\text{ADD, SUB}$ and $\text{MOV}$. Consider $2$ ... and by how many $\text{MOV}$ instructions? $\text{Case 2,2}$ $\text{Case 2,3}$ $\text{Case 1,2}$ $\text{Case 1,3}$
asked Jan 13, 2020 in CO and Architecture Satbir 1k views
0 votes
1 answer
14
computer organization
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to ... instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.
Consider the hypothetical processor is supports both 2 address and one address instructions. It has 128-word memory A 16-bit instruction is placed in the one memory word. Q1.What is the range of two address and one address instructions are supported? A)1 to 3 and 128 ... address instructions can be supported? A)128 B)2 C)256 D)32 PLEASE GIVE SOLUTION IN DETAILED MANNER...ESPECIALLY FOR PART 1.
asked Feb 1, 2019 in CO and Architecture learner_geek 1.5k views
1 vote
0 answers
15
MadeEasy Test Series 2019: CO & Architecture - Machine Instruction
Q.A stack based CPU executes the instruction.Memory location 500 contains 0x88 and memory location 700 contains 0x37.The stack pointer is at 0x003F. The instructions are as follows: I1:PUSH 500 I2:PUSH 700 I3:ADD ... after execution instructions c)Memory location 600 contains 0xBF after execution instructions d)Both (a) and (c)
Q.A stack based CPU executes the instruction.Memory location 500 contains 0x88 and memory location 700 contains 0x37.The stack pointer is at 0x003F. The instructions are as follows: I1:PUSH 500 I2:PUSH 700 I3:ADD I4:POP 600 I5:PUSH 300 Which of the ... )Memory location 0x40 contain 0x88 after execution instructions c)Memory location 600 contains 0xBF after execution instructions d)Both (a) and (c)
asked Jan 20, 2019 in CO and Architecture Badayayash 757 views
2 votes
3 answers
16
Self Doubt
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?
Consider a hypothetical CPU which supports 2 address, 1 address and 0 address instructions. A 16 bit instruction is placed in 128 word memory. If there exists 2 two address instructions and 100 one address instructions, then how many 0 address instructions can be designed?
asked Jan 19, 2019 in CO and Architecture Rishav Chetan 333 views
0 votes
0 answers
17
MadeEasy Full Length Test 2019: CO & Architecture - Machine Instructions
A stack based CPU executes the instruction. Memory location 500 contain 0x88 and memory location 700 contains 0x37. The stack pointer is at 0x003F. The instructions are as follows: $I_1 -$ PUSH 500 $I_2 -$ PUSH 700 $I_ 3-$ ... in to use Ginger Limited mode $I_2: PUSH300$ Log in to use Ginger Limited mode $I_2: $PUSH300
A stack based CPU executes the instruction. Memory location 500 contain 0x88 and memory location 700 contains 0x37. The stack pointer is at 0x003F. The instructions are as follows: $I_1 -$ PUSH 500 $I_2 -$ PUSH 700 $I_ 3-$ ADD $I_4- $ POP 600 $I_5 -$ PUSH 300 ... approve all of its suggestions. Log in to use Ginger Limited mode $I_2: PUSH300$ Log in to use Ginger Limited mode $I_2: $PUSH300
asked Jan 16, 2019 in CO and Architecture shreyansh jain 308 views
0 votes
1 answer
20
AAI JE (IT) 2018 - Q74
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.
How are 2 memory access required here? Only R3 contains a memory address which will be accessed for the operand.
asked Dec 13, 2018 in CO and Architecture shaz 267 views
2 votes
1 answer
21
RISC processor doubt
is the CPI of RISC processor always 1?
is the CPI of RISC processor always 1?
asked Dec 10, 2018 in CO and Architecture aditi19 624 views
0 votes
0 answers
23
adressing modes
For Given machine instructions LW R4 #400 L1:LW R1, 0,(R4) LW R2 400(R4) ADDI R3, R1, R2 SW R3, 0(R4) SUB R4, R4, #4 BNZ R4, L1 on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?
For Given machine instructions LW R4 #400 L1:LW R1, 0,(R4) LW R2 400(R4) ADDI R3, R1, R2 SW R3, 0(R4) SUB R4, R4, #4 BNZ R4, L1 on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?
asked Nov 10, 2018 in CO and Architecture rishabhdevsingh1 279 views
0 votes
1 answer
24
adressing modes
Given 2 machine instructions, LW R4 #400 LW R1, 0,(R4) IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory location operand..I want to clarify weather value stored in register is same as adress that register points.
Given 2 machine instructions, LW R4 #400 LW R1, 0,(R4) IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory location operand..I want to clarify weather value stored in register is same as adress that register points.
asked Nov 9, 2018 in CO and Architecture rishabhdevsingh1 305 views
1 vote
1 answer
25
Computer Organization
Consider the following program segment used to execute on a hypothetical processor. Consider all the registers are of 16 bit size I1 MOV CX,0005 ; CX ← 0005 I2 MOV BX,OFF7H ; BX ← OFF7H I3 MOV AX,OBCAH ; AX ← OBCAH I4 OR BX,AX ; BX ← ... 4 cycles and transfer of control operations takes 2 cycles to execute. How much time is required to execute the program on a above CPU?
Consider the following program segment used to execute on a hypothetical processor. Consider all the registers are of 16 bit size I1 MOV CX,0005 ; CX ← 0005 I2 MOV BX,OFF7H ; BX ← OFF7H I3 MOV AX,OBCAH ; AX ← OBCAH I4 OR BX,AX ; BX ← BX (OR) ... operations takes 4 cycles and transfer of control operations takes 2 cycles to execute. How much time is required to execute the program on a above CPU?
asked Sep 2, 2018 in CO and Architecture Sumit Singh Chauhan 931 views
3 votes
1 answer
26
Computer Organization
A computer has 256 K word memory. The instruction format has 4 fields i.e., Opcode, register field to represent one of the 60 processor registers, mode field represent one of 7 addressing modes and memory address field. How many instructions the system supports when a 32- bit instruction is placed in the one memory cell.
A computer has 256 K word memory. The instruction format has 4 fields i.e., Opcode, register field to represent one of the 60 processor registers, mode field represent one of 7 addressing modes and memory address field. How many instructions the system supports when a 32- bit instruction is placed in the one memory cell.
asked Sep 2, 2018 in CO and Architecture Sumit Singh Chauhan 3k views
3 votes
2 answers
27
Instruction Addressing
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB
A computer has 170 different operations. Word size is 4 bytes one word instructions requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ______________(in KB). Ans. 256KB
asked Jul 31, 2018 in CO and Architecture Na462 936 views
2 votes
1 answer
28
RISC Instruction set
Assume that RISC processor contains 10 global registers, 10 local registers, 6 In registers and 6 Out register. It contain 4 register windows. What is the size of window and register file of the processor? Ans. 32 and 74 Please Explain the Formula and what's the meaning of Window size and register file in RISC Processor ?
Assume that RISC processor contains 10 global registers, 10 local registers, 6 In registers and 6 Out register. It contain 4 register windows. What is the size of window and register file of the processor? Ans. 32 and 74 Please Explain the Formula and what's the meaning of Window size and register file in RISC Processor ?
asked Jul 27, 2018 in CO and Architecture Na462 2.1k views
1 vote
4 answers
29
Instruction Execution
Consider the 2 GHz clock frequency processor used execute the following program segment. Assume the 3 clock cycles required for Register to/from memory transfer, 1 clock cycle for ADD with both operands in register, 2 clock cycle MUL with both operands in ... for instruction fetch and decode. What is the total time required to complete the program execution (in ns)? Ans. 18
Consider the 2 GHz clock frequency processor used execute the following program segment. Assume the 3 clock cycles required for Register to/from memory transfer, 1 clock cycle for ADD with both operands in register, 2 clock cycle MUL with both operands in register, 3 clock ... word for instruction fetch and decode. What is the total time required to complete the program execution (in ns)? Ans. 18
asked Jul 21, 2018 in CO and Architecture Na462 678 views
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