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Recent questions tagged madeeasy-testseries-2019

1 vote
1 answer
1
Suppose a queue $Q$ and two stacks $S_{1}$ and $S_{2}$ as given below. void enqueue(Q,x){ push(S1,x); } void dequeue(Q,x){ if(stack-empty(S2))then if(stack-empty(S1))then{ print("Q is empty"); return; } else while(!stack-empty(S1)){ x= ... is equal to______________ $Enqueue(4),Enqueue(3),Enqueue(2),Dequeue, Enqueue(6),Dequeue,Dequeue, Dequeue,Enqueue(5)$ Please tell value of X and Y are u getting
asked Apr 24, 2019 in Programming srestha 189 views
0 votes
2 answers
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Consider the function give below, which should return the index of first zero in input array of length $n$ if present else return $-1.$ int index of zero(int[ ] array,int n){ for(int i=0; P ;i++); if(i==n){ return -1; } return i; } What should be placed in place code at ‘P’,So that code will work fine? $A)$array[i]!=0 && i<=n $B)$ array[i]!=0 && i<n
asked Apr 24, 2019 in Programming srestha 220 views
1 vote
1 answer
3
Consider a simple undirected weighted graph G(V, E) with 10 vertices and 45 edge, assume (u, v) are two vertices weight of a edge is =4lu- vl then the minimum cost of the spanning tree of G_ 36
asked Jan 30, 2019 in Algorithms Ram Swaroop 577 views
3 votes
1 answer
4
Consider a n-way cache with 'x blocks of 64 words each. The main memory of the system is having 8 million words. Size of the tag field is 16 bits and additional memory required for tags is 1024 bytes. What will be the values of n and x respectively? Answer 256 512
asked Jan 30, 2019 in CO and Architecture Ram Swaroop 513 views
0 votes
1 answer
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Consider the following C code: #include <stdio.h> struct MadeEasy { char p,q,r; }; int main (void) { struct MadeEasy a={ d' - 2019,'e',5+'a'}; struct MadeEasy *b=&a; printf("%c, %c", *((char*)b+1)- 1, *((char*)b+ 2)- 1); return 0; } The output of the following code will be
asked Jan 29, 2019 in Programming Ram Swaroop 248 views
2 votes
1 answer
7
A CPU cache is organized into 2 level cache L1 and L2 The penalty for L1 cache miss and L2 cache miss are 60 and 30 respectively for 1200 memory references The hit time of L1 and L2 are 5 and 10 clock cycles and penalty for L2 cache miss to main memory is 70 clock cycles. The average memory access time will be
asked Jan 29, 2019 in CO and Architecture Ram Swaroop 496 views
1 vote
0 answers
10
A 1 Mbps satellite link connects two ground stations. The altitude of the satellite is 6000 km and speed of the signal is 3 10^8 m/s. What should be the packet size for a channel utilization of 50% for a satellite link using go-back-63 ... that the acknowledgment packets are negligible in size and that there are no errors during communication. 81031 Bytes 83101 Bytes 801301 Bytes 81301 Bytes
asked Jan 28, 2019 in Computer Networks Badayayash 311 views
2 votes
0 answers
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Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1)
asked Jan 28, 2019 in CO and Architecture snaily16 279 views
1 vote
1 answer
15
Let L = {w| w ∈ {0,1}*; w contains 01 and 011 as substring}. The number of states in the minimal DFA corresponding to the complement of L is equal to My Answer: Correct if I am wrong. Its complement will be all strings which don’t have 01 as substring. so if we make its dfa then minimum number of states will be 3. Answer given is 4
asked Jan 28, 2019 in Theory of Computation Mayank Bansal 271 views
2 votes
0 answers
16
Q.Consider a 2 dimensional array A[40 ... 95, 40 ... 95] in lower triangular matrix representation. If the array is implemented in the memory in the form of row major order and base address of the array is 1000, then the address of A[66][50] will be ________.
asked Jan 27, 2019 in Programming Badayayash 295 views
0 votes
0 answers
17
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1 answer
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Consider the hashing table with 'm' slots and 'n' keys. If the expected number of probes in unsuccessful search is 3. The expected number of probes in a successful search is_ Answer 1.647
asked Jan 27, 2019 in DS Ram Swaroop 495 views
2 votes
0 answers
19
0 votes
3 answers
23
Consider the system which has the virtual address of 36 bits and physical address of 30 bits and page size of 8 kb, page table entry contains 1 valid bit, 2 protection bit and 1 reference bit. Then the approximate page table size in MB is_________. My doubt does we always take page table entry as nearest bytes, or sometimes we consider it as bits also. If yes, then in what case we take it as bits.
asked Jan 25, 2019 in Operating System CSHuB 275 views
1 vote
0 answers
26
Consider a source computer (S) transmitting a file of size $2 * 10^6$ bits to a destination computer (D) over a network of three routers ($R_1$, $R_2$ and $R_3$) and four links $(L_1, L_2, L_3 and L_4)$. $L_1$ connects $S$ to $R_1$; $L_2$ connects $R_1$ to ... the total sum of transmission and propagation delays in transmitting the file from $S$ to $D$? a. 1007 ms b. 1010 ms c. 2010 ms d 2007 ms
asked Jan 24, 2019 in Computer Networks CSHuB 150 views
0 votes
1 answer
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