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Recent questions tagged memory-interfacing
1
votes
1
answer
61
co - memory interface query,whether to do or not
Do we need to practise memory interfacing (not given in syllabus) questions? but people are actively answering questions here on memory interface. If yes, what types might come?
Do we need to practise memory interfacing (not given in syllabus) questions? but people are actively answering questions here on memory interface. If yes, what types migh...
resilientknight
606
views
resilientknight
asked
Aug 16, 2016
CO and Architecture
memory-interfacing
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–
1
votes
2
answers
62
total size of memory system
A memory system has a total of 8 memory chips each with 12 address lines and 4 data lines. The total size of memory system is a) 6 KB b)32 KB c)48 KB d)64 KB
A memory system has a total of 8 memory chips each with 12 address lines and 4 data lines. The total size of memory system isa) 6 KB b)32 KB c)48 KB d)64 KB
komal07
4.4k
views
komal07
asked
Jun 27, 2016
CO and Architecture
memory-interfacing
+
–
7
votes
3
answers
63
ISRO2011-54
Number of chips $(128 \times 8 \;\text{RAM})$ needed to provide a memory capacity of $2048$ bytes $2$ $4$ $8$ $16$
Number of chips $(128 \times 8 \;\text{RAM})$ needed to provide a memory capacity of $2048$ bytes$2$$4$$8$$16$
go_editor
4.6k
views
go_editor
asked
Jun 23, 2016
CO and Architecture
isro2011
co-and-architecture
memory-interfacing
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–
5
votes
2
answers
64
ISRO2014-40
Assume that $16$-bit CPU is trying to access a double word stating at an odd address. How many memory operations are required to access the data? $1$ $2$ $3$ $4$
Assume that $16$-bit CPU is trying to access a double word stating at an odd address. How many memory operations are required to access the data?$1$$2$$3$$4$
Sourabh Kumar
5.8k
views
Sourabh Kumar
asked
Jun 22, 2016
CO and Architecture
isro2014
co-and-architecture
memory-interfacing
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–
8
votes
2
answers
65
ISRO2007-37
In comparison with static RAM memory, the dynamic Ram memory has lower bit density and higher power consumption higher bit density and higher power consumption lower bit density and lower power consumption higher bit density and lower power consumption
In comparison with static RAM memory, the dynamic Ram memory haslower bit density and higher power consumptionhigher bit density and higher power consumptionlower bit den...
go_editor
7.1k
views
go_editor
asked
Jun 10, 2016
CO and Architecture
isro2007
co-and-architecture
memory-interfacing
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–
6
votes
2
answers
66
ISRO2009-23
The process of organizing the memory into two banks to allow $8$-and $16$-bit data operation is called Bank switching Indexed mapping Two-way memory interleaving Memory segmentation
The process of organizing the memory into two banks to allow $8$-and $16$-bit data operation is calledBank switchingIndexed mappingTwo-way memory interleavingMemory segme...
Desert_Warrior
3.3k
views
Desert_Warrior
asked
Jun 3, 2016
CO and Architecture
isro2009
co-and-architecture
memory-interfacing
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–
3
votes
2
answers
67
How many RAM chips & size of decoder required?
How many 256 X 4 RAM chips are required to organize a memory of capacity 32KB ? What is the size of decoder required in this implementation to select a row of chip? Options : (a) 128 , 7 X 128 (b) 256 , 7 X 128 (c) 512 , 7 X 128 (d) 256 , 8 X 256.
How many 256 X 4 RAM chips are required to organize a memory of capacity 32KB ? What is the size of decoder required in this implementation to select a row of chip?Option...
Jitendra Verma
13.6k
views
Jitendra Verma
asked
Mar 14, 2016
CO and Architecture
co-and-architecture
memory-interfacing
out-of-syllabus-now
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–
23
votes
4
answers
68
GATE CSE 2016 Set 1 | Question: 09
A processor can support a maximum memory of $4\;\textsf{GB}$, where the memory is word-addressable (a word consists of two bytes). The size of address bus of the processor is at least _________bits.
A processor can support a maximum memory of $4\;\textsf{GB}$, where the memory is word-addressable (a word consists of two bytes). The size of address bus of the processo...
Sandeep Singh
12.4k
views
Sandeep Singh
asked
Feb 12, 2016
CO and Architecture
gatecse-2016-set1
co-and-architecture
easy
numerical-answers
memory-interfacing
+
–
13
votes
5
answers
69
ISRO2015-77
In $\text{X = (M + N }\times \text{O)/(P} \times \text{Q})$, how many one-address instructions are required to evaluate it? $4$ $6$ $8$ $10$
In $\text{X = (M + N }\times \text{O)/(P} \times \text{Q})$, how many one-address instructions are required to evaluate it?$4$$6$$8$$10$
Purple
7.0k
views
Purple
asked
Jan 26, 2016
CO and Architecture
memory-interfacing
co-and-architecture
machine-instruction
isro2015
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–
1
votes
0
answers
70
Gate 2016 syllabus C.O. memory interface
Memory Interface topic has been removed. Can someone tell me what kind question will not be asked. or what not to do in this section?
Memory Interface topic has been removed. Can someone tell me what kind question will not be asked.or what not to do in this section?
Pradip Nichite
725
views
Pradip Nichite
asked
Jan 13, 2016
CO and Architecture
co-and-architecture
memory-interfacing
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–
1
votes
1
answer
71
Made easy CA q16
How many 512k x 8 static RAM chips are needed to design the 2M x 32 memory module. a. 32 b. 8 c.16 d.64
How many 512k x 8 static RAM chips are needed to design the 2M x 32 memory module.a. 32 b. 8 c.16 d.64
khushtak
4.6k
views
khushtak
asked
Oct 19, 2015
CO and Architecture
co-and-architecture
memory-interfacing
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–
0
votes
2
answers
72
How to calculate which memory block will go in which block in set associative cache?
If there is k-set associative cache, with total x cache blocks, and 2^n main memory locations, how is the mapping calculated?
If there is k-set associative cache, with total x cache blocks, and 2^n main memory locations, how is the mapping calculated?
Tehreem
1.0k
views
Tehreem
asked
Sep 22, 2015
CO and Architecture
cache-memory
co-and-architecture
memory-interfacing
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–
12
votes
5
answers
73
ISRO2014-1
Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for additional circuitry like buffering and decoding. $0$ $1$ $2$ $3$
Consider a $33$ MHz cpu based system. What is the number of wait states required if it is interfaced with a $60$ ns memory? Assume a maximum of $10$ ns delay for addition...
ajit
8.6k
views
ajit
asked
Sep 8, 2015
CO and Architecture
co-and-architecture
isro2014
memory-interfacing
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–
7
votes
2
answers
74
ISRO2014-25
Suppose you want to build a memory with $4$ byte words and a capacity of $2^{21}$ bits. What is type of decoder required if the memory is built using $2K \times$ $8$ $\text{RAM}$ chips? $\text{5 to 32}$ $\text{6 to 64}$ $\text{4 to 16}$ $\text{7 to 128}$
Suppose you want to build a memory with $4$ byte words and a capacity of $2^{21}$ bits. What is type of decoder required if the memory is built using $2K \times$ $8$ $\te...
ajit
6.6k
views
ajit
asked
Aug 15, 2015
Digital Logic
digital-logic
memory-interfacing
isro2014
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–
10
votes
6
answers
75
ISRO2014-17
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4 \times 6$ array, where each chip is $8\;\text{K} \times 4$ bits? $13$ $15$ $16$ $17$
If each address space represents one byte of storage space, how many address lines are needed to access RAM chips arranged in a $4 \times 6$ array, where each chip is $8\...
ajit
10.3k
views
ajit
asked
Aug 15, 2015
CO and Architecture
co-and-architecture
memory-interfacing
isro2014
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–
0
votes
2
answers
76
How many 256 X 4 RAM chips are needed to organize a memory of capacity of 32KB?
Shefali
20.2k
views
Shefali
asked
Aug 8, 2015
CO and Architecture
co-and-architecture
memory-interfacing
ram
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–
5
votes
2
answers
77
How many 2K x 8 RAM chips are needed?
We want to build a memory with 4-byte words and a capacity of 221 bits. How many 2K x 8 RAM chips are needed? How many address lines are needed for the memory? How many of these address lines are connected to the address inputs of the RAM chips? How many of these address lines ... to 32 256, 16, 11, 5, 5 to 32 128, 16, 10, 6, 6 to 64 512, 15, 10, 5, 5 to 32
We want to build a memory with 4-byte words and a capacity of 221 bits. How many 2K x 8 RAM chips are needed? How many address lines are needed for the memory? How many o...
Supromit Roy
19.9k
views
Supromit Roy
asked
Dec 1, 2014
CO and Architecture
memory-interfacing
ram
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–
37
votes
4
answers
78
GATE IT 2005 | Question: 9
A dynamic RAM has a memory cycle time of $64$ $\text{nsec}$. It has to be refreshed $100$ times per msec and each refresh takes $100$ $\text{nsec}$ . What percentage of the memory cycle time is used for refreshing? $10$ $6.4$ $1$ $0.64$
A dynamic RAM has a memory cycle time of $64$ $\text{nsec}$. It has to be refreshed $100$ times per msec and each refresh takes $100$ $\text{nsec}$ . What percentage of t...
Ishrat Jahan
10.5k
views
Ishrat Jahan
asked
Nov 3, 2014
Digital Logic
gateit-2005
digital-logic
memory-interfacing
normal
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–
29
votes
3
answers
79
GATE CSE 1995 | Question: 2.2
The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are needed for a memory of $4K \times 16$? $10$ address, $16$ data lines $11$ address, $8$ data lines $12$ address, $16$ data lines $12$ address, $12$ data lines
The capacity of a memory unit is defined by the number of words multiplied by the number of bits/word. How many separate address and data lines are needed for a memory of...
Kathleen
11.6k
views
Kathleen
asked
Oct 8, 2014
Digital Logic
gate1995
digital-logic
memory-interfacing
normal
+
–
53
votes
2
answers
80
GATE CSE 2010 | Question: 7
The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1\text{M} \times \text{1-bit}$ DRAM chips. Each DRAM chip has $1\text{K}$ rows of cells with $1\text{K}$ cells in each row. The time taken for a single ... in the memory unit is $100$ nanoseconds $100\times 2^{10}$ nanoseconds $100\times 2^{20}$ nanoseconds $3200\times 2^{20}$ nanoseconds
The main memory unit with a capacity of $4$ $\text{megabytes}$ is built using $1\text{M} \times \text{1-bit}$ DRAM chips. Each DRAM chip has $1\text{K}$ rows of cells wit...
go_editor
18.8k
views
go_editor
asked
Sep 29, 2014
Digital Logic
gatecse-2010
digital-logic
memory-interfacing
normal
+
–
44
votes
4
answers
81
GATE CSE 2006 | Question: 41
A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive banks with wrap-around. All the $k$ banks can be accessed in parallel, but two ... the latency of retrieving a cache block starting at address zero from main memory is: $92$ ns $104$ ns $172$ ns $184$ ns
A CPU has a cache with block size $64$ bytes. The main memory has $k$ banks, each bank being $c$ bytes wide. Consecutive $c$ − byte chunks are mapped on consecutive ban...
Rucha Shelke
14.0k
views
Rucha Shelke
asked
Sep 26, 2014
CO and Architecture
gatecse-2006
co-and-architecture
cache-memory
memory-interfacing
normal
+
–
24
votes
6
answers
82
GATE CSE 2009 | Question: 7, ISRO2015-3
How many $32K \times 1$ RAM chips are needed to provide a memory capacity of $ 256K$ bytes? $8$ $32$ $64$ $128$
How many $32K \times 1$ RAM chips are needed to provide a memory capacity of $ 256K$ bytes?$8$$32$$64$$128$
Kathleen
17.5k
views
Kathleen
asked
Sep 22, 2014
Digital Logic
gatecse-2009
digital-logic
memory-interfacing
easy
isro2015
+
–
2
votes
0
answers
83
GATE CSE 1992 | Question: 06,a,b
A microprocessor is capable of addressing 1 megabyte of memory with a 20-bit address bus. The system to be designed requires 256 K bytes of RAM, 256 K bytes of EPROM, 16 I/O devices (memory mapped I/O) and 1 K byte of ... to two clock cycles for memory read and write. Assuming control signals similar to 8085, design the extra logic required for interfacing EERAM.
A microprocessor is capable of addressing 1 megabyte of memory with a 20-bit address bus. The system to be designed requires 256 K bytes of RAM, 256 K bytes of EPROM, 16 ...
Kathleen
1.0k
views
Kathleen
asked
Sep 13, 2014
Digital Logic
gate1992
digital-logic
descriptive
memory-interfacing
out-of-gate-syllabus
8085-microprocessor
+
–
2
votes
2
answers
84
GATE CSE 1991 | Question: 01,ii
In interleaved memory organization, consecutive words are stored in consecutive memory modules in _______ interleaving, whereas consecutive words are stored within the module in ________ interleaving.
In interleaved memory organization, consecutive words are stored in consecutive memory modules in _______ interleaving, whereas consecutive words are stored within the mo...
Kathleen
2.5k
views
Kathleen
asked
Sep 12, 2014
CO and Architecture
gate1991
co-and-architecture
normal
memory-interfacing
+
–
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