Recent questions tagged memory-management

Recent questions tagged memory-management

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1 answer

1

Gate Applied Test Series
Question: Consider a system using a segmented paging architecture. The segment is divided into 8k pages each of size 2k words . The segment table is divided into 256 k pages each of size 512 words. The page table entry size requires 64 bits . The frame number requires 22 bits ... address (LA). Note: 1 Word = 1 Byte Options Are: A. 51 bits B. 61 bits C. 33 bits D. 64 bits

lalitver10 asked in Operating System Jan 11

74 views

0 votes

1 answer

2

Memory Management
In a virtual memory system, size of the virtual address is 32-bit, size of the physical address is 30-bit, page size is 4 KByte and size of each page table entry is 32-bit. The main memory is word addressable and word size is 4Bytes. Find the maximum number of bits that can be used for storing other information ?

Vidya Sagar asked in Operating System Jan 3

44 views

1 vote

2 answers

3

Gate Applied course Test series
What is answer for this question and also please explain the approach

Dheeraj Varma asked in Operating System Nov 16, 2021

by Dheeraj Varma

265 views

4 votes

1 answer

4

Applied Test Series
Please help me in understanding this question

LRU asked in Operating System Nov 7, 2021

by LRU

227 views

0 votes

1 answer

5

Applied Test Series
An operating system implements a single level paging. This system uses Translation Lookaside Buffer (TLB) and Physical Address Cache (PAC) as well. TLB has a hit ratio 90%. PAC has a miss ratio of 20%. Main memory access time, TLB access time and ... ns respectively. Assuming that all the pages of the process are in main memory, the effective memory access time is ______ (ns).

LRU asked in Operating System Nov 3, 2021

by LRU

182 views

1 vote

0 answers

6

Page Table Entries in page Table
In Page Table,page-frame address entries are static or Dynamic means whether they are changed or not??(Consider 1-level page table)

lalitver10 asked in Operating System Oct 21, 2021

159 views

1 vote

1 answer

7

Applied Practice test
Suppose: TLB lookup time = 20 ns TLB hit ratio = 80% Memory access time = 75 ns PFST = 500,000 ns 50% of the pages are dirty OS uses a single level page table What is the approximated effective access time (EAT) if we assume the page fault rate is 10%? Assume the cost to update the TLB, the page table, and the frame table (if needed) is negligible.

darshak_devani asked in Operating System Oct 18, 2021

by darshak_devani

211 views

2 votes

0 answers

8

Applied Test Series
A hypothetical system OSXZ_09 implements paging. Given LAS = 4 GB, PAS = 64 MB, Page size = 4 KB. A protection bit and a reference bit is also present in a page table entry. Then the size of the innermost page table is ____ B. Note : The memory is byte addressable.

LRU asked in Operating System Oct 11, 2021

by LRU

143 views

16 votes

4 answers

9

GATE CSE 2021 Set 2 | Question: 48
Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below: The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)$ and page table entry size at every level is $8$ bytes. A ... $P$ across all levels is _________ $\text{KB}$.

Arjun asked in Operating System Feb 18, 2021

by Arjun

7.6k views

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