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Recent questions tagged memory-management

7 votes
3 answers
1
Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below: The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)$ and page table entry size at every level is $8$ bytes. A process $P$ is currently ... $2\text{GB}$ of physical memory. The minimum amount of memory required for the page table of $P$ across all levels is _________ $\text{KB}$.
asked Feb 18 in Operating System Arjun 2k views
3 votes
2 answers
2
If there are $32$ segments, each of size $1$ K byte, then the logical address should have $13 \text{ bits}$ $14 \text{ bits}$ $15 \text{ bits}$ $16 \text{ bits}$
asked Apr 2, 2020 in Operating System Lakshman Patel RJIT 496 views
3 votes
2 answers
5
1 vote
1 answer
6
2 votes
2 answers
7
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a Translation Look-aside Buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$
asked Mar 30, 2020 in Operating System Lakshman Patel RJIT 379 views
1 vote
4 answers
8
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit
asked Mar 30, 2020 in Operating System Lakshman Patel RJIT 1.1k views
2 votes
3 answers
9
A memory management system has $64$ pages with $512$ bytes page size. Physical memory consists of $32$ page frames Number of bits required in logical and physical address are respectively: $14$ and $15$ $14$ and $29$ $15$ and $14$ $16$ and $32$
asked Mar 24, 2020 in Operating System jothee 481 views
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