# Recent questions tagged memory-management

1
Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below: The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)$ and page table entry size at every level is $8$ bytes. A process $P$ is currently ... $2\text{GB}$ of physical memory. The minimum amount of memory required for the page table of $P$ across all levels is _________ $\text{KB}$.
2
If there are $32$ segments, each of size $1$ K byte, then the logical address should have $13 \text{ bits}$ $14 \text{ bits}$ $15 \text{ bits}$ $16 \text{ bits}$
1 vote
3
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer
4
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer
5
If a processor has $32$-bit virtual address, $28$-bit physical address, $2$ kb pages. How many bits are required for the virtual, physical page number? $17,21$ $21,17$ $6,10$ None
1 vote
6
Copying a process from memory to disk to allow space for other processes is called: Swapping Demand Paging Deadlock Page Fault
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a Translation Look-aside Buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$
A memory management system has $64$ pages with $512$ bytes page size. Physical memory consists of $32$ page frames Number of bits required in logical and physical address are respectively: $14$ and $15$ $14$ and $29$ $15$ and $14$ $16$ and $32$