Recent questions tagged memory-management

11 votes

3 answers

1

GATE CSE 2021 Set 2 | Question: 48
Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below: The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)$ and page table entry size at every level is $8$ bytes. A ... $P$ across all levels is _________ $\text{KB}$.

Arjun asked in Operating System Feb 18

by Arjun

3.7k views

3 votes

2 answers

2

NIELIT 2016 MAR Scientist C - Section C: 8
If there are $32$ segments, each of size $1$ K byte, then the logical address should have $13 \text{ bits}$ $14 \text{ bits}$ $15 \text{ bits}$ $16 \text{ bits}$

Lakshman Patel RJIT asked in Operating System Apr 2, 2020

by Lakshman Patel RJIT

775 views

1 vote

1 answer

3

NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 5
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

316 views

4 votes

3 answers

4

NIELIT 2017 OCT Scientific Assistant A (CS) - Section C: 2
Which of the following is not a form of main memory? Instruction cache Instruction register Instruction opcode Translation look-aside buffer

Lakshman Patel RJIT asked in CO and Architecture Apr 1, 2020

by Lakshman Patel RJIT

343 views

3 votes

2 answers

5

NIELIT 2017 OCT Scientific Assistant A (CS) - Section B: 4
If a processor has $32$-bit virtual address, $28$-bit physical address, $2$ kb pages. How many bits are required for the virtual, physical page number? $17,21$ $21,17$ $6,10$ None

Lakshman Patel RJIT asked in Operating System Apr 1, 2020

by Lakshman Patel RJIT

346 views

1 vote

1 answer

6

NIELIT 2016 DEC Scientist B (IT) - Section B: 51
Copying a process from memory to disk to allow space for other processes is called: Swapping Demand Paging Deadlock Page Fault

Lakshman Patel RJIT asked in Operating System Mar 31, 2020

by Lakshman Patel RJIT

1k views

2 votes

2 answers

7

NIELIT 2017 July Scientist B (CS) - Section B: 32
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a Translation Look-aside Buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$

Lakshman Patel RJIT asked in Operating System Mar 30, 2020

by Lakshman Patel RJIT

499 views

1 vote

2 answers

8

NIELIT 2017 DEC Scientist B - Section B: 16
Which of the following is added to the page table in order to track whether a page of cache has been modified since it was read from the memory? Reference bit Dirty bit Tag bit Valid bit

Lakshman Patel RJIT asked in Operating System Mar 30, 2020

by Lakshman Patel RJIT

1.2k views

2 votes

3 answers

9

UGCNET-Jan2017-III: 49
A memory management system has $64$ pages with $512$ bytes page size. Physical memory consists of $32$ page frames Number of bits required in logical and physical address are respectively: $14$ and $15$ $14$ and $29$ $15$ and $14$ $16$ and $32$

jothee asked in Operating System Mar 24, 2020

by jothee

559 views

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