Recent questions tagged operand-forwarding

+1 vote

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Self Doubt
How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .

asked Feb 18 in CO and Architecture by DIYA BASU (233 points) | 84 views

0 votes

1 answer

2

Data forwarding in pipelining
Data forwarding is used to avoid which type of conflict?? (1) RAW (2) WAR (3) WAW (4) RAR

asked Jan 2 in CO and Architecture by Abhilash Mishra (115 points) | 160 views

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3

MadeEasy Test Series: CO & Architecture - Pipelining
here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)

asked Dec 25, 2018 in CO and Architecture by Markzuck Junior (667 points) | 196 views

+1 vote

0 answers

4

https://gateoverflow.in/753/gate2001-12?show=279851#c279851
doubt in this gate question- https://gateoverflow.in/753/gate2001-12?show=279851#c279851 In instruction I3 how is it getting the value of r2 which is computed in I1 instruction?? Can memory access stage read the value of updated register values of write back stage?? please resolve my doubt.

asked Dec 18, 2018 in CO and Architecture by sushmita Boss (17.3k points) | 82 views

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0 answers

5

general doubt on pipelining
we do forwarding from WB stage to EX or from WB to MEM stage??

asked Dec 18, 2018 in CO and Architecture by sushmita Boss (17.3k points) | 69 views

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0 answers

6

MadeEasy Test Series: CO & Architecture - Pipelining
The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction output present at 4th stage and ALU instruction output is at third stage. Assume each stage ... must be inserted to achieve CPI = 1 by using Operand Forwarding ? A. 3 B. 4 C. 5 D. 6

asked Oct 13, 2018 in CO and Architecture by Na462 Loyal (6.9k points) | 168 views

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7

Operand Forwarding Doubt
I dont understand here:- Load R2,(R3) 1. Fetch 2. Decode: Rz <--- Address of R3 given in instruction 3. Compute : NOP 4. Memory Memory address <---[RZ] , read memory, Ry <---MemData 5. R2 <--- [Ry] If i wrote above right then R2 is available at Cycle 5 but there is extra stall at cycle 6 for Instruction j+1 why ??

asked Sep 3, 2018 in CO and Architecture by Na462 Loyal (6.9k points) | 145 views

+2 votes

0 answers

8

#Data Hazards #Operand Forwarding #CO
Is there any difference in calculating data hazards and dependencies? Doubt 1:I've read that in data dependencies calculation we chose adjacent instructions only? IS THIS TRUE. Doubt 2:Calculation of RAW,WAR,WAW hazards include all ... adjacent.IS THIS TRUE There are many sources which are confusing Please Explain how to calculate dependencies and hazards.

asked Jan 13, 2018 in CO and Architecture by Deepak Mokili (217 points) | 131 views

+1 vote

1 answer

9

Doubt in Pipelining Terminology
In pipelining questions we have "If operand forwarding is there " and "If operand forwarding is not there " Please explain this difference and how to draw the chart for both the cases .

asked Dec 10, 2017 in CO and Architecture by Parshu gate Active (3.1k points) | 95 views

+1 vote

1 answer

10

Pipeline
Give answer for question no. 12 please! provide detailed answer.

asked Oct 15, 2017 in CO and Architecture by learner_geek Active (3.2k points) | 194 views

+2 votes

0 answers

11

Dealing with ALU-ALU forwarding
Consider two instruction sequences: a. SW R16,-100(R6) LW R4, 8(R16) ADD R5,R4,R4 b. OR R1,R2,R3 OR R2,R1,R3 OR R1,R1,R2 Add NOP instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage).

asked Jun 26, 2017 in CO and Architecture by GateAspirant999 Active (2.5k points) | 505 views

+1 vote

1 answer

12

Pipeline
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4th stage ALU instruction output ... What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.

asked Feb 4, 2017 in CO and Architecture by srestha Veteran (117k points) | 312 views

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1 answer

13

Pipeline

asked Jan 29, 2017 in CO and Architecture by monty Junior (843 points) | 72 views

+1 vote

1 answer

14

pipeline bypassing
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO ... number of clock cycles needed to execute the following sequence of instruction where operand forwarding from WO to PO and PO to OF is used

asked Jan 25, 2017 in CO and Architecture by Pankaj Joshi Active (2.6k points) | 447 views

+12 votes

1 answer

15

Operand forwarding in pipeline
A $5$ stage pipelined processor has the following stages: $IF$ : instruction fetch $ID$ : instruction decode $EX$ : execute $MA$ : memory access $WB$ ... No. of cycles needed to execute these instructions using operand forwarding?

asked Jan 8, 2017 in CO and Architecture by dd Veteran (57k points) | 4.8k views

+1 vote

1 answer

16

no data forwarding
Consider the following sequence of instructions executed on the five-stage pipelined processor: I1: lw $1, 40($6) I2: add $2, $3, $1 I3: add $1, $2, $6 I4: sw $2, 20($4) I5 : and $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?

asked Nov 2, 2016 in CO and Architecture by Akriti sood Boss (12.2k points) | 230 views

0 votes

1 answer

17

MadeEasy Test Series: CO & Architecture - Pipelining
they have not given the number of cycles taken by ADD/LOAD..i have taken as 1..correct if i am wrong The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume ... available in 3rd stage. Assume each stage take 1 cycle. What is the number of cycles are saved by using operand forwarding.

asked Jan 28, 2016 in CO and Architecture by sourav. Boss (16.1k points) | 224 views

0 votes

2 answers

18

MadeEasy Test Series: CO & Architecture - Pipelining
please check the answer...

asked Jan 22, 2016 in CO and Architecture by sourav. Boss (16.1k points) | 451 views

+2 votes

0 answers

19

MadeEasy Test Series: CO & Architecture - Pipelining
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output ... cycle. What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.

asked Jan 19, 2016 in CO and Architecture by khushtak Loyal (7k points) | 290 views

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