# Recent questions tagged operand-forwarding

1 vote
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How many cycle required when pipelining and operand loading is used? R1<-R2+R3 R4<-R1+M[100] Value at M[100]=7 There are 5 phases: F->TO FETCH D->TO DECODE AND OPERAND READ E->EXECUTE M->MEMORY ACCESS W->WRITE BACK Each phase takes 1Cycle .
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Data forwarding is used to avoid which type of conflict?? (1) RAW (2) WAR (3) WAW (4) RAR
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here why to take stall at the highlighted cell as its OPERAND FORWARDING and unless mentioned its EX-EX and its being followed without stall also, please clarify how to understand where Operand Forwarding is to be applied in such generalized cases., Thanks in advance :)
1 vote
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doubt in this gate question- https://gateoverflow.in/753/gate2001-12?show=279851#c279851 In instruction I3 how is it getting the value of r2 which is computed in I1 instruction?? Can memory access stage read the value of updated register values of write back stage?? please resolve my doubt.
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we do forwarding from WB stage to EX or from WB to MEM stage??
1 vote
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The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction output present at 4th stage and ALU instruction output is at third stage. Assume each stage takes one cycle. How many instructions must be inserted to achieve CPI = 1 by using Operand Forwarding ? A. 3 B. 4 C. 5 D. 6
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I dont understand here:- Load R2,(R3) 1. Fetch 2. Decode: Rz <--- Address of R3 given in instruction 3. Compute : NOP 4. Memory Memory address <---[RZ] , read memory, Ry <---MemData 5. R2 <--- [Ry] If i wrote above right then R2 is available at Cycle 5 but there is extra stall at cycle 6 for Instruction j+1 why ??
8
Is there any difference in calculating data hazards and dependencies? Doubt 1:I've read that in data dependencies calculation we chose adjacent instructions only? IS THIS TRUE. Doubt 2:Calculation of RAW,WAR,WAW hazards include all instructions as a whole not only adjacent.IS THIS TRUE There are many sources which are confusing Please Explain how to calculate dependencies and hazards.
1 vote
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In pipelining questions we have "If operand forwarding is there " and "If operand forwarding is not there " Please explain this difference and how to draw the chart for both the cases .
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Consider two instruction sequences: a. SW R16,-100(R6) LW R4, 8(R16) ADD R5,R4,R4 b. OR R1,R2,R3 OR R2,R1,R3 OR R1,R1,R2 Add NOP instructions to this code to eliminate hazards if there is ALU-ALU forwarding only (no forwarding from the MEM to the EX stage).
1 vote
12
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4th stage ALU instruction output is ... What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.
13
A $5-$ stage pipelined processor has IF,ID,EX,MEM and WB . WB stage operation is divided into two parts. In the first part register write operation and in second part register read operation is performed. The latency of those stages are $300,400,500,500,300$ (in nano seconds) respectively.Consider ... $I_{4}$ SUB $R_{1},R_{7},R_{4}$ $R_{1} <- R_{7} - R_{4}$ The program execution time__________ns?
1 vote
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A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO stage takes 1 ... The number of clock cycles needed to execute the following sequence of instruction where operand forwarding from WO to PO and PO to OF is used
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A $5$ stage pipelined processor has the following stages: $IF$ : instruction fetch $ID$ : instruction decode $EX$ : execute $MA$ : memory access $WB$ : write back $\large\color{red}{IF \rightarrow ID\rightarrow EX\rightarrow MA\rightarrow WB}$ Each stage needs ... No. of cycles needed to execute these instructions using operand forwarding?
1 vote
16
Consider the following sequence of instructions executed on the five-stage pipelined processor: I1: lw $1, 40($6) I2: add $2,$3, $1 I3: add$1, $2,$6 I4: sw $2, 20($4) I5 : and $1,$1, \$4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?