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Recent questions tagged operand-forwarding
1
votes
1
answer
31
pipeline bypassing
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO ... number of clock cycles needed to execute the following sequence of instruction where operand forwarding from WO to PO and PO to OF is used
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, O...
Pankaj Joshi
2.2k
views
Pankaj Joshi
asked
Jan 25, 2017
CO and Architecture
operand-forwarding
co-and-architecture
pipelining
+
–
17
votes
1
answer
32
Operand forwarding in pipeline
A $5$ stage pipelined processor has the following stages: $IF$ : instruction fetch $ID$ : instruction decode $EX$ : execute $MA$ : memory access $WB$ ... No. of cycles needed to execute these instructions using operand forwarding?
A $5$ stage pipelined processor has the following stages:$IF$ : instruction fetch$ID$ : instruction decode$EX$ : execute$MA$ : memory access$WB$ : write back$$\large\colo...
dd
21.0k
views
dd
asked
Jan 8, 2017
CO and Architecture
pipelining
co-and-architecture
operand-forwarding
+
–
1
votes
1
answer
33
no data forwarding
Consider the following sequence of instructions executed on the five-stage pipelined processor: I1: lw $1, 40($6) I2: add $2, $3, $1 I3: add $1, $2, $6 I4: sw $2, 20($4) I5 : and $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?
Consider the following sequence of instructions executed on the five-stage pipelined processor:I1: lw $1, 40($6)I2: add $2, $3, $1I3: add $1, $2, $6I4: sw $2, 20($4)I5 : ...
Akriti sood
824
views
Akriti sood
asked
Nov 1, 2016
CO and Architecture
pipelining
operand-forwarding
co-and-architecture
+
–
0
votes
1
answer
34
MadeEasy Test Series: CO & Architecture - Pipelining
they have not given the number of cycles taken by ADD/LOAD..i have taken as 1..correct if i am wrong The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume ... available in 3rd stage. Assume each stage take 1 cycle. What is the number of cycles are saved by using operand forwarding.
they have not given the number of cycles taken by ADD/LOAD..i have taken as 1..correct if i am wrongThe following sequence of instruction is executed in a basic 5 stage p...
sourav.
580
views
sourav.
asked
Jan 28, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
operand-forwarding
+
–
0
votes
2
answers
35
MadeEasy Test Series: CO & Architecture - Pipelining
please check the answer...
please check the answer...
sourav.
912
views
sourav.
asked
Jan 22, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
operand-forwarding
+
–
2
votes
1
answer
36
MadeEasy Test Series: CO & Architecture - Pipelining
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output ... cycle. What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resol...
khushtak
596
views
khushtak
asked
Jan 19, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
operand-forwarding
+
–
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