Recent questions tagged paging / GATE Overflow for GATE CSE

0 votes

1 answer

241

Paging

Shah

1.3k views

Shah asked Dec 17, 2016

5 votes

1 answer

242

find the page table size
Consider the following memory organization of a processor. The virtual address is 40 bits, the physical address is 32 bits, the page size is 8 KB. The processor has a 4-way set associative 128-entry TLB i.e. each way has 32 sets. Each page table entry is ... way set associative 32 KB L1 cache with line size of 64 bytes. What is the total size of the page table? 8MB 10MB 2MB

Consider the following memory organization of a processor. The virtual address is 40 bits, the physical address is 32 bits, the page size is 8 KB. The processor has a 4-w...

Akriti sood

4.9k views

Akriti sood asked Dec 14, 2016

2 votes

1 answer

243

Memory Management
Main memory is partition into Chunks in I. Simple Paging. II. Virtual memory Paging III. Simple segmentation. IV. Virtual memory segmentation a) I & II b) I & III c) I, II and III d) All Ans::(a) is it Correct..?

Main memory is partition into Chunks inI. Simple Paging.II. Virtual memory PagingIII. Simple segmentation.IV. Virtual memory segmentationa) I & II ...

Meghashyam Sujay

2.7k views

Meghashyam Sujay asked Dec 12, 2016

0 votes

1 answer

244

ace operating system
Answer given is B, but I think it should be D. Stack will pop the least recently used page from the top. How can having most recently used page on top help in LRU implementation?

Answer given is B, but I think it should be D. Stack will pop the least recently used page from the top. How can having most recently used page on top help in LRU impleme...

Purple

745 views

Purple asked Nov 29, 2016

1 votes

1 answer

245

page table modification
Should we have to change the mode while modifying the page table?

Should we have to change the mode while modifying the page table?

vaishali jhalani

913 views

vaishali jhalani asked Nov 26, 2016

1 votes

1 answer

246

paging os
In a two level paging environment a page table is divided into 2^12 pages each of size 4 KW. The memory is word addressable, The physical address space is 128 MW. Memory is divided into 2^14 frames. Length of the logical address is(in bits) __________

In a two level paging environment a page table is divided into 2^12 pages each of size 4 KW. The memory is word addressable, The physical address space is 128 MW. Memory ...

focus _GATE

1.7k views

focus _GATE asked Nov 25, 2016

2 votes

1 answer

247

NPTEL Worked out Problem | Page Replacement
If the total number of available frames is 50, and there are 2 processes one of 10 pages and the other of 5 pages then how much of memory would be proportionally allocated to each of these processes? a. Depends on the ... allocated equally for both d. 5 and 10 respectively Source: http://nptel.ac.in/courses/106108101/pdf/Worked_Out_Problems/Mod_4.pdf

If the total number of available frames is 50, and there are 2 processes one of 10 pages and the other of 5 pages then how much of memory would be proportionally allocate...

agoh

4.1k views

agoh asked Nov 10, 2016

5 votes

2 answers

248

Operating System
Consider a Memory Management System where TLB hit rate is 90% whose access time is 1 cycle. The hit ratio for cache is 80% and if access time is 1 cycle. The page fault rate when there is a miss in both TLB and cache is 2%. Main ... and cache acesses are sequential. The average memory access time when the cache is virtually addressed is __________ cycle. (Upto 2 decimal places)

Consider a Memory Management System where TLB hit rate is 90% whose access time is 1 cycle. The hit ratio for cache is 80% and if access time is 1 cycle. The page fault r...

srestha

3.5k views

srestha asked Oct 17, 2016

1 votes

2 answers

249

memory management

vaishali jhalani

778 views

vaishali jhalani asked Oct 11, 2016

3 votes

1 answer

250

memory management

vaishali jhalani

1.1k views

vaishali jhalani asked Oct 7, 2016

4 votes

4 answers

251

UGC NET CSE | August 2016 | Part 3 | Question: 51
An operating system supports a paged virtual memory, using a central processor with a cycle time of one microsecond. It costs an additional one microsecond to access a page other than the current one. Pages have $1000$ words, ... and the processor is idle during drum transfers ? $30$ microseconds $34$ microseconds $60$ microseconds $68$ microseconds

An operating system supports a paged virtual memory, using a central processor with a cycle time of one microsecond. It costs an additional one microsecond to access a pa...

makhdoom ghaya

6.5k views

makhdoom ghaya asked Oct 4, 2016

9 votes

4 answers

252

paging
Q. Suppose you have a computer system with a 48-bit logical address, page size of 16KB and 4 bytes per page table entry. If we have a 48MB program such that the entire program and all necessary page tables are in memory. Assume that each page table at diff level fits in a single page.How much memory is used by program, including its page tables?

Q.Suppose you have a computer system with a 48-bit logical address, page size of 16KB and 4 bytes per page table entry. If we have a 48MB program such that the entire pro...

Akriti sood

6.8k views

Akriti sood asked Oct 3, 2016

3 votes

3 answers

253

OS : page table
Account for the validity and justification about the correctness of this statement " Whatever level page table is always the nuber of bits which are going to refer a frame number will always going to be same "

Account for the validity and justification about the correctness of this statement" Whatever level page table is always the nuber of bits which are going to refer a frame...

pC

554 views

pC asked Oct 3, 2016

3 votes

0 answers

254

paging
Suppose you have a computer system with a 48-bit logical address, page size of 16K and 4 bytes per page table entry. If we have a 48MB program such that the entire program and all necessary page tables are in memory. How much memory is used by program, including its page tables? 216(3111) 216(3121) 28(3121) 210(3121)

Suppose you have a computer system with a 48-bit logical address, page size of 16K and 4 bytes per page table entry. If we have a 48MB program such that the entire progra...

Shashank Chandekar

1.1k views

Shashank Chandekar asked Oct 2, 2016

6 votes

1 answer

255

paging
Consider a system using multi level paging environment. Address bits are segregated as follows: Here first 8 bits represent the required bits for first level, next 8 bits represent the required bits for second level, next 6 bits represent the required bits for third level ... process that has 512 K of memory starting at address 0? Assume each page table entry is 4 bytes. 2048 3192 1024 4096

Consider a system using multi level paging environment. Address bits are segregated as follows: Here first 8 bits represent the required bits for first level, next 8 bits...

Shashank Chandekar

1.4k views

Shashank Chandekar asked Oct 1, 2016

2 votes

1 answer

256

paging
Consider a processor has virtual address 52 bits, the physical address is 32 bits and the page size is 16KB. Each individual table at any level of the page table occupies a single page of physical memory. Using multi level paging, how many entries are there in each individual page table page ... purpose? < 2, 12, 12, 12 > <10,14,14,14> <4,14,14,14> <10,12,14,14>

Consider a processor has virtual address 52 bits, the physical address is 32 bits and the page size is 16KB. Each individual table at any level of the page table occupies...

Shashank Chandekar

1.4k views

Shashank Chandekar asked Oct 1, 2016

2 votes

0 answers

257

tanenbaum OS
Compute the run time of a program which has 55.500.000 memory accesses, a TLB hit rate of 75%, and a page fault rate of 0,005. We consider the TLB access time negligible. The page fault rate is the percent of memory accesses that require a disk access. ... TLB miss, the OS accesses the memory to get the page table entry and updates the TLB. Which is the run time of the application??

Compute the run time of a program which has 55.500.000 memory accesses, a TLB hit rate of 75%, and a page fault rate of 0,005. We consider the TLB access time negligible....

sushmita

439 views

sushmita asked Oct 1, 2016

3 votes

0 answers

258

OS : Paging
In a 32-bit machine we subdivide the virtual address into 4 segments as follows: 10-bit 8-bit 6-bit 8 bit We use a 3-level page table, such that the first 10-bit are for the first level and so on. Page Table Entry Size is 2B What ... 0x80000000 and a stack segment of 64K starting at address 0xf0000000 and growing upward What would be the change when the memory is nibble addressable ?

In a 32-bit machine we subdivide the virtual address into 4 segments as follows: 10-bit8-bit6-bit8 bitWe use a 3-level page table, such that the first 10-bit are for the ...

pC

597 views

pC asked Oct 1, 2016

4 votes

1 answer

259

made easy test
A computer system with 2 level paging scheme in which regular memory access takes 300 nanoseconds and servicing a pagefault takes 500ns. An average instruction takes 200 ns of CPU time and one memory access. The TLB hit ratio is 80% and page fault ratio is 20%. The average instruction execution time is ? My answer is 660 ns but made easy solution has 580 ns. Can any one check??

A computer system with 2 level paging scheme in which regular memory access takes 300 nanoseconds and servicing a pagefault takes 500ns. An average instruction takes 200 ...

sushmita

1.7k views

sushmita asked Sep 29, 2016

1 votes

3 answers

260

#Operating Systems (Silberschatz, Galvin, Gagne) #VirutalMemory #Page325
In this problem I have a doubt that why effective access time is not taken as effective access time = 1 x 200 + p x (8 milliseconds) because even though pages are accessed after page-fault but all pages must be ... (p x 8 milliseconds) to bring page from disk to memory, plus, 200 nanoseconds for accessing all pages in memory

In this problem I have a doubt that why effective access time is not taken as effective access time = 1 x 200 + p x (8 milliseconds)because even though pages are accessed...

PratikLatve

874 views

PratikLatve asked Sep 28, 2016

3 votes

1 answer

261

Operating System
Consider a simple paging system with the following characteristics: a page table size of 64 entries of 11 bits (including valid/invalid bit )each and a page size of 512 bytes. (a) How many bits in the logical address specify the page number? (b) How many bits ... the size of logical address? (d) How many bits are there in physical address? (e) What is the size of physical address?

Consider a simple paging system with the following characteristics: a page table size of 64 entries of 11 bits (including valid/invalid bit )each and a page size of 512 b...

सुमित सिंह

4.7k views

सुमित सिंह asked Sep 24, 2016

0 votes

0 answers

262

UGC NET CSE | December 2010 | Part 2 | Question: 39
Page making process from main memory to disk is called Interruption Termination Swapping None of the above

Page making process from main memory to disk is calledInterruptionTerminationSwappingNone of the above

makhdoom ghaya

1.4k views

makhdoom ghaya asked Sep 9, 2016

0 votes

1 answer

263

easy and tricky co question

resilientknight

387 views

resilientknight asked Sep 3, 2016

2 votes

3 answers

264

GATE Overflow | Operating Systems | Test 1 | Question: 13
In a paged memory, the page hit ratio is 0.35. The time required to access a page in secondary memory is 100 ns. The time required to access a page in primary memory is 10 ns. The average time required to access a page is 100 ns 68.0 ns 68.5 ns 78.5 ns

In a paged memory, the page hit ratio is 0.35. The time required to access a page in secondary memory is 100 ns. The time required to access a page in primary memory is 1...

Bikram

824 views

Bikram asked Sep 3, 2016

1 votes

2 answers

265

Operating System

shikhar_deep05

442 views

shikhar_deep05 asked Aug 21, 2016

8 votes

1 answer

266

Question related to: gate 2008_67Here is the question: https://gateoverflow.in/490/gate2008_67?show=61309#c61309"So, in the given question, a main memory page frame is fe...

resilientknight

2.3k views

resilientknight asked Aug 1, 2016

1 votes

1 answer

267

operating system-paging
"In a 32-bit machine we subdivide the virtual address into 4 segments as follows: [10-bit 8-bit 6-bit 8 bit] We use a 3-level page table, such that the first 10-bit are for the first level and so on. What is the size of a page table for a process that ... , 2+ (2*16) + (2^6*2)*16. please clear my concept. should we take the entire page table size and not just the entry?

"In a 32-bit machine we subdivide the virtual address into 4 segments as follows:[10-bit 8-bit 6-bit 8 bit]We use a 3-level page table, such that the first 10-bit are for...

resilientknight

1.1k views

resilientknight asked Jul 31, 2016

1 votes

1 answer

268

os multilevel paging
I am not able to understand the concept of multilevel paging.plz can someone tell what is stored in 1st level and 2nd level page table and how do we access it??

I am not able to understand the concept of multilevel paging.plz can someone tell what is stored in 1st level and 2nd level page table and how do we access it??

jenny101

852 views

jenny101 asked Jul 25, 2016

4 votes

1 answer

269

UGC NET CSE | December 2014 | Part 2 | Question: 39
For the implementation of a paging scheme, suppose the average process size be $x$ bytes, the page size be $y$ bytes, and each page entry requires $z$ bytes. The optimum page size that minimizes the total overhead due to the page table and the internal fragmentation loss is given by $\frac{x}{2}$ $\frac{xz}{2}$ $\sqrt{2xz}$ $\frac{\sqrt{xz}}{2}$

For the implementation of a paging scheme, suppose the average process size be $x$ bytes, the page size be $y$ bytes, and each page entry requires $z$ bytes. The optimum ...

makhdoom ghaya

4.4k views

makhdoom ghaya asked Jul 23, 2016

3 votes

1 answer

270

UGC NET CSE | June 2013 | Part 3 | Question: 59
A job has four pages A, B, C, D and the main memory has two page frames only. The job needs to process its pages in following order: ABACABDBACD Assuming that the page interrupt occurs when a new page is brought in the main memory, ... number of page interrupts in FIFO and LRU page replacement algorithms are 9 and 7 7 and 6 9 and 8 8 and 6

A job has four pages A, B, C, D and the main memory has two page frames only. The job needs to process its pages in following order:ABACABDBACDAssuming that the page inte...

go_editor

2.6k views

go_editor asked Jul 18, 2016

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