Recent questions tagged pipelining / GATE Overflow for GATE CSE

2 votes

2 answers

211

Pipelining

Na462

2.1k views

Na462 asked Nov 7, 2018

0 votes

0 answers

212

made easy co tt1
I THINK ANSWER SHOULD BE 462,THEY HAVE GIVEN ANSWER 554, WHICH I FEEL IS WRONG!

I THINK ANSWER SHOULD BE 462,THEY HAVE GIVEN ANSWER 554, WHICH I FEEL IS WRONG!

Gate Fever

692 views

Gate Fever asked Nov 6, 2018

0 votes

0 answers

213

Self Doubt
In this question, https://gateoverflow.in/69709/pipelining Kapil Sir had commented that we can do split phase access between memory access(MA) stage and execute(EX) stage of a pipeline..but how is split phase access possible here? As far as i know, memory ... in this link https://gateoverflow.in/252781/operand-forwarding Can we use split phase access between MA and EX stage in this case?

In this question, https://gateoverflow.in/69709/pipelining Kapil Sir had commented that we can do split phase access between memory access(MA) stage and execute(EX) stag...

Somoshree Datta 5

455 views

Somoshree Datta 5 asked Nov 5, 2018

0 votes

0 answers

214

SELF DOUBT
PLEASE explain what is operand forwarding and how we are going to implement this in stages during execution of the instruction ??? and also when to use it in according to question property and not when to use it ? pls check these questions of same concept also ... this phenomena . i am not getting it if someone got the link of operand forwarding from where should i hv done this plzz add

PLEASE explain what is operand forwarding and how we are going to implement this in stages during execution of the instruction ???and also when to use it in according to...

Deepanshu

288 views

Deepanshu asked Nov 3, 2018

0 votes

0 answers

215

test series
A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take 1 clock cycle each for any instruction. The PO stage ... above sequence of instructions? my answer comes 16 cycle please tell where i did wrong but answer given is 17 please elaborate with figure

A 5-stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, O...

Anshu Singh Suryavan

349 views

Anshu Singh Suryavan asked Nov 3, 2018

0 votes

0 answers

216

SELF DOUBT
S1 S2 S3 S4 I1: 1 2 1 2 I2: 2 1 2 1 I3: 1 1 2 1 I4: 2 1 2 1 Consider a pipeline processor with 4 stages S1 to S4. We want to execute the following loop for (i = 1; i < = 10; i++) {I1, I2, I3, I4} The output of I1 for i = 2 will be available after 11 ns 12ns 13 ns 28 ns

S1S2S3S4I1:1212I2:2121I3:1121I4:2121 Consider a pipeline processor with 4 stages S1 to S4. We want to execute the following loopfor (i = 1; i < = 10; i++) {I1, I2, I3, I4...

Deepanshu

683 views

Deepanshu asked Nov 2, 2018

0 votes

0 answers

217

ACE TEST SERIES QUESTION

Shankar Kakde

146 views

Shankar Kakde asked Nov 2, 2018

3 votes

1 answer

218

Gateforum Test Series: CO & Architecture - Pipelining

Gupta731

305 views

Gupta731 asked Nov 2, 2018

2 votes

1 answer

219

Gateforum Test Series: CO & Architecture - Pipelining

Gupta731

267 views

Gupta731 asked Nov 2, 2018

0 votes

1 answer

220

made easy test series
ans given is 1.92

ans given is 1.92

amitqy

431 views

amitqy asked Nov 1, 2018

0 votes

0 answers

221

Doubt clearing
Incase of operand forwarding in RISC pipeline with stages Instruction fetch (IF) Instruction decode (ID) Execute (EX) Memory Access (MA) Write Back (WB) If it is not mentioned from which stage to which stage the operand is forwarded, should I by default take that it is forwarded from MA stage to ID stage?

Incase of operand forwarding in RISC pipeline with stages Instruction fetch (IF)Instruction decode (ID)Execute (EX)Memory Access (MA)Write Back (WB)If it is not mentioned...

nepobose

190 views

nepobose asked Oct 31, 2018

0 votes

0 answers

222

CO & Architecture - Pipelining
Design a binary multiply pipeline unit for two 4 bit operands.Use minimum number of CSA's and CPA's.Show all interconnections and bus width in the schematic diagram.Calculate the output of each CSA and CPA for A=11111111 and B=11111111

Design a binary multiply pipeline unit for two 4 bit operands.Use minimum number of CSA's and CPA's.Show all interconnections and bus width in the schematic diagram.Calcu...

LavTheRawkstar

307 views

LavTheRawkstar asked Oct 31, 2018

2 votes

1 answer

223

Pipeline : Number of RAW dependencies
Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding. I1: ADD R0,R1,R2 (R0=R1+R2) I2: SUB R3,R0,R2 I3:MUL R4,R3,R0 I4:DIV R5,R4,R0 How many RAW dependencies?

Consider the below instructions executed on a 5 stage(IF,ID,EX,MA,WB) RISC pipeline with operand forwarding.I1: ADD R0,R1,R2 (R0=R1+R2)I2: SUB R3,R0,R2I3:MUL R4,R3,R0I4:D...

Mk Utkarsh

2.3k views

Mk Utkarsh asked Oct 23, 2018

1 votes

1 answer

224

DOUBT: isn't this is a pipelining question
How to do these questions? there is no information about no. of stages an instruction takes? Consider the 2 GHz clock frequency processor used execute the following program segment. Assume the 3 clock cycles required for Register to/from memory transfer, 1 ... the total time required to complete the program execution (in ns)? A) 12 B) 15 C) 18 D) 25

How to do these questions? there is no information about no. of stages an instruction takes? Consider the 2 GHz clock frequency processor used execute the following progr...

Ashwani Yadav

514 views

Ashwani Yadav asked Oct 18, 2018

0 votes

1 answer

225

Test_CO1_Q35
Assume branch instruction occurs 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forwarding, the load delay slot is one cycle and can be filled 60% if the time with useful instructions, 20% of the ... What is the new CPI due to load delay slots and branch hazards? A. 1.204 B. 1.404 C. 2.204 D. 4.404

Assume branch instruction occurs 15% of the time and are predicted as not taken, while in practice they are taken 40% of the time with a penalty of 3 cycles. With forward...

BOB

271 views

BOB asked Oct 15, 2018

1 votes

1 answer

226

MadeEasy Test Series: CO & Architecture - Pipelining
The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction output present at 4th stage and ALU instruction output is at third stage. Assume each stage ... must be inserted to achieve CPI = 1 by using Operand Forwarding ? A. 3 B. 4 C. 5 D. 6

The following sequence of instructions is executed in basic 5 stage pipeline ( F D E M W). Assume data dependency is resolved by Operand Forwarding. Load instruction outp...

Na462

997 views

Na462 asked Oct 13, 2018

0 votes

0 answers

227

Pipelining
Approach :

Approach :

HeadShot

391 views

HeadShot asked Oct 7, 2018

0 votes

1 answer

228

Addressing modes + pipelining
I got Option D , and Are we saving 1 cycle by replacement ? ( if yes then may be solved it correct else i am wrong somewhere )

I got Option D , and Are we saving 1 cycle by replacement ? ( if yes then may be solved it correct else i am wrong somewhere )

HeadShot

361 views

HeadShot asked Oct 4, 2018

1 votes

0 answers

229

Is superscalar operations in pipelining part of gate syllabus
Is superscalar operations in pipelining part of gate syllabus?

Is superscalar operations in pipelining part of gate syllabus?

bts1jimin

472 views

bts1jimin asked Oct 4, 2018

0 votes

1 answer

230

Branch prediction in pipelining part of syllabhs?
Is branch prediction in pipelining im Co and architecture part of gate syllabus?

Is branch prediction in pipelining im Co and architecture part of gate syllabus?

bts1jimin

767 views

bts1jimin asked Oct 3, 2018

1 votes

0 answers

231

Pipeline performance reduced if different stages have different execution delays
The pipeline performance is reduced if the different stages of a pipeline have different delays I know that in the pipeline, Tclock is taken as the Max(Ti)+Tbuffer time, and so, if the pipeline ... that having different delays for the different stages of the pipeline will affect the performance. Please explain ?

The pipeline performance is reduced if the different stages of a pipeline have different delaysI know that in the pipeline, Tclock is taken as the Max(Ti)+Tbuffer time, a...

Harsh Kumar

342 views

Harsh Kumar asked Oct 2, 2018

3 votes

1 answer

232

Minimum clock cycle

Na462

1.6k views

Na462 asked Sep 24, 2018

0 votes

0 answers

233

#CO pipeline doubt
Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of cycles needed to execute the following loop? For (i=1 to 2){I1; I2; ... stage, the current instruction(I4) cannot execute a given stage P.S.- Refer here- https://gateoverflow.in/244642/%23co-gate-2009-self-doubt

Consider a 4 stage pipeline processor. The number of cycles needed by the four instructions I1, I2, I3, I4 in stages S1, S2, S3, S4 is shown below: What is the number of...

iarnav

832 views

iarnav asked Sep 21, 2018

0 votes

1 answer

234

UNDEFINED
in a 5 stage pipeline processor a program consist of 50 instruction suppose there are 20% instruction require 1 extra stall cycle what is the cpi from this execution ?

in a 5 stage pipeline processor a program consist of 50 instruction suppose there are 20% instruction require 1 extra stall cycle what is the cpi from this execution ?

noblesarkar

209 views

noblesarkar asked Sep 19, 2018

0 votes

0 answers

235

#CO Gate 2009 Self Doubt.
Original question- https://gateoverflow.in/1314/gate2009-28 In the best answer selected, why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stage? In this question if we take the above approach, we will get different ... Refer this GATE 2004-IT question- https://gateoverflow.in/3690/gate2004-it-47 in this we are doing as the above approach.

Original question- https://gateoverflow.in/1314/gate2009-28In the best answer selected, why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stag...

iarnav

235 views

iarnav asked Sep 19, 2018

0 votes

0 answers

236

Self Doubt : Pipe lining
Given 100 instructions executed on a 5 stage pipeline . probability (p) that an instruction is branch is p. Branch penalty 4.Assuming that each stage of pipeline takes 1 cycle.Calculate total execution time. My query is since first instruction will take 5 clk so how to calculate ? is 5+ 99[(1-p)*1 + p*4] the correct approach ?

Given 100 instructions executed on a 5 stage pipeline . probability (p) that an instruction is branch is p. Branch penalty 4.Assuming that each stage of pipeline takes 1 ...

Shiv Gaur

293 views

Shiv Gaur asked Sep 8, 2018

0 votes

0 answers

237

Operand Forwarding Doubt
I dont understand here:- Load R2,(R3) 1. Fetch 2. Decode: Rz <--- Address of R3 given in instruction 3. Compute : NOP 4. Memory Memory address <---[RZ] , read memory, Ry <---MemData 5. R2 <--- [Ry] If i wrote above right then R2 is available at Cycle 5 but there is extra stall at cycle 6 for Instruction j+1 why ??

I dont understand here:- Load R2,(R3)1. Fetch2. Decode: Rz < - Address of R3 given in instruction3. Compute : NOP4. Memory Memory address < -[RZ] , read memory, Ry < -Mem...

Na462

1.2k views

Na462 asked Sep 3, 2018

0 votes

1 answer

238

Pipeline Doubt
Its a snapshot from hamacher. According to me there should be stall of 2 cycles why 3 ?? Because after Write stage the data will be available in register file so why extra stall in 6th clock cycle ?

Its a snapshot from hamacher.According to me there should be stall of 2 cycles why 3 ??Because after Write stage the data will be available in register file so why extra ...

Na462

909 views

Na462 asked Sep 3, 2018

1 votes

1 answer

239

COA -INSTRUCTION PIPELINE
Consider a 4 stage pipeline:fetch-IF(2cycle), decode& read -ID(1 cycle) execute-Ex(4 cycle for multiply and 7 cycle for divide ,1 cycle for all other arithmatic operations ) and Write Back WB(1 cycle) . Assume that in a program A there ... divides,85% of othe types of instructions that take 1 cycle in execute stage . How many cycle does it take to execute program A?

Consider a 4 stage pipeline:fetch-IF(2cycle), decode& read -ID(1 cycle) execute-Ex(4 cycle for multiply and 7 cycle for divide ,1 cycle for all other arithmatic operation...

gourav94240

775 views

gourav94240 asked Aug 28, 2018

1 votes

0 answers

240

Patterson-Henessey, Pipelining
Here, in the DADDI instruction, there are only two stalls. But since there is no operand forwarding, won't the contents of the register be available after they've been written into the register file and so, there should be three stalls? ... I could understand in this question, the value of the registers is available after the M stage, before it is written.

Here, in the DADDI instruction, there are only two stalls. But since there is no operand forwarding, won't the contents of the register be available after they've been wr...

goxul

292 views

goxul asked Aug 17, 2018

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