Recent questions tagged pipelining / GATE Overflow for GATE CSE

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331

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 26
Which of the following statements is/are correct about hazards? One way to implement branch prediction is to store the result of a branch condition in a branch target buffer to help guide instruction pre-fetching if the branch is ... whether the branch is taken. III only II and III only I and III only I, II, and III

Which of the following statements is/are correct about hazards?One way to implement branch prediction is to store the result of a branch condition in a branch target buff...

Bikram

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Bikram asked May 27, 2017

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2 answers

332

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 21
Consider a $5$ stage instruction pipeline which can implement the $4$ instructions $I1, \ I2, \ I3, \ I4$ ... The speed up of the pipeline is approximately ________

Consider a $5$ stage instruction pipeline which can implement the $4$ instructions $I1, \ I2, \ I3, \ I4$. Below table gives the number of clocks required per instruction...

Bikram

398 views

Bikram asked May 27, 2017

2 votes

2 answers

333

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 20
Suppose there are $m$ instructions to be executed in a program. $p$ is the probability that an instruction is a conditional branch instruction, and $q$ is the probability of a successful branch. Assume the average number of instructions completed in a simple ... $pq (mn -1) + p( 1- q) mn$ $1 +pq ( n - 1)$ $p - pq$

Suppose there are $m$ instructions to be executed in a program. $p$ is the probability that an instruction is a conditional branch instruction, and $q$ is the probabilit...

Bikram

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Bikram asked May 27, 2017

1 votes

1 answer

334

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 19
Consider the following two types of Cache Designs : Cache $1$: It is a direct-mapped cache with eight $1$ - word cache lines. The miss penalty is $8$ clock cycles. Cache $2$ : It is a two-way associative cache with ... cycles and Cache $2$ spends $60$ cycles Cache $1$ spends $56$ cycles and Cache $2$ spends $70$ cycles

Consider the following two types of Cache Designs : Cache $1$: It is a direct-mapped cache with eight $1$ – word cache lines. The miss penalty is $8$ clock cycles.Cache...

Bikram

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Bikram asked May 27, 2017

1 votes

1 answer

335

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 17
Consider a pipelined system with these $4$ phases: FI - Fetch instruction DA - Decode and calculate address FO - Fetch Operand EX- Execute instruction Each phase requires one clock cycle. There were four ... exists pipeline hazards , then the number of clock cycles required to complete the above program is _________

Consider a pipelined system with these $4$ phases:FI – Fetch instructionDA – Decode and calculate addressFO – Fetch OperandEX- Execute instructionEach phase requi...

Bikram

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Bikram asked May 27, 2017

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1 answer

336

Test by Bikram | Computer Organization and Architecture | Test 2 | Question: 13
What is the total number of Read after Write (RAW), Write after Read (WAR) and Write after Write (WAW) dependencies, respectively in the following assembly program? ... $2,1,3$ $3,1,2$ $1,2,3$ $3,2,1$

What is the total number of Read after Write (RAW), Write after Read (WAR) and Write after Write (WAW) dependencies, respectively in the following assembly program?$\begi...

Bikram

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Bikram asked May 27, 2017

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1 answer

337

#CSO_pipelining
In flow dependency, instructions level parallelism is possible or not ? How many type of dependency is possible in pipelining ?

In flow dependency, instructions level parallelism is possible or not ?How many type of dependency is possible in pipelining ?

elakashi sharma

286 views

elakashi sharma asked May 15, 2017

1 votes

1 answer

338

Test by Bikram | Mock GATE | Test 4 | Question: 28
There is an $RISC$ processor which uses pipeline technique. Within the processor, all the arithmetic instructions have the same $CPI$ (cycles per instruction). Which of the following actions would improve the execution time of an arithmetically ... and the data cache without changing the clock cycle time. II only I and III III only I and II

There is an $RISC$ processor which uses pipeline technique. Within the processor, all the arithmetic instructions have the same $CPI$ (cycles per instruction).Which of th...

Bikram

487 views

Bikram asked May 14, 2017

0 votes

2 answers

339

Hazard in Pipelining
Consider the Program segment I1: r0 <- r1 + r2; I2: r2 <- r0 * r3; I3: r0 <- r2 / r0; I4: r3 <- r2 * r0; I5: M[x] <- r3; Q1> Calculate the number of - 1. Read after write hazard 2. Write after Read hazard 3. Write after Write hazard. Q2> which of these hazards happen between the two adjacents instructions.

Consider the Program segmentI1: r0 <- r1 + r2;I2: r2 <- r0 * r3;I3: r0 <- r2 / r0;I4: r3 <- r2 * r0;I5: M[x] <- r3;Q1 Calculate the number of - 1. Read after write haz...

Shubhanshu

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Shubhanshu asked Apr 30, 2017

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1 answer

340

ISI-JRF
A machine M has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses: F-stage - instruction fetch (9 ns), D-stage - instruction decode and register fetch (3 ns), X-stage - execute/address ... , where every 3rd instruction needs a 1-cycle stall before the X-stage. Calculate the CPU time in seconds for completing P.

A machine M has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses:F-stage — instruction fetch (9 n...

kauray

482 views

kauray asked Apr 20, 2017

1 votes

2 answers

341

ISRO 2008-ECE Pipeline
Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is (a) $2N$ (b) $N^ 2$ (c) $N$ (d) $N!$

Assuming ideal conditions, the speed up obtained from a balanced N stage pipeline is(a) $2N$(b) $N^ 2$(c) $N$(d) $N!$

sh!va

673 views

sh!va asked Mar 2, 2017

2 votes

1 answer

342

ISRO2010-ECE Pipeline Hazard
Consider the following assembly code for a hypothetical RISC processor with a $4$-stage pipeline (Instruction Fetch, Decode/Register Read, Execute and Write). add r1,r2,r3 // r1 = r2+r3 sub r4,r1,r3 //r4 = r1 - r3 mul r5,r2, ... . Read after write hazard during mul Read after write hazard during sub Read after write hazard during add Write after write hazard during mul

Consider the following assembly code for a hypothetical RISC processor with a $4$-stage pipeline (Instruction Fetch, Decode/Register Read, Execute and Write).add r1,r2,r3...

sh!va

714 views

sh!va asked Feb 28, 2017

1 votes

1 answer

343

ISRO2015-EC Pipelining
Pipelining technique is used in microprocessor to improve which of the following parameter? Power dissipation Interrupt latency Die size Maximum clock frequency

Pipelining technique is used in microprocessor to improve which of the following parameter?Power dissipationInterrupt latencyDie sizeMaximum clock frequency

sh!va

929 views

sh!va asked Feb 22, 2017

44 votes

8 answers

344

GATE CSE 2017 Set 1 | Question: 50
Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). These stages take 5, 4, 20, 10 and 3 nanoseconds (ns) ... speedup (correct to two decimal places) achieved by EP over NP in executing $20$ independent instructions with no hazards is _________ .

Instruction execution in a processor is divided into $5$ stages, Instruction Fetch (IF), Instruction Decode (ID), Operand fetch (OF), Execute (EX), and Write Back (WB). T...

khushtak

19.2k views

khushtak asked Feb 14, 2017

2 votes

1 answer

345

#GATE2017_1
Consider a five stage pipeline having stages IF,ID,OF,EX and WB having stage delays 5,6,14,20 and 8 ns. Buffer delay is 2 ns.(say this is pipeline design 1). Now in this design, if we break the EX stage into 2 stages having delays 12ns and 8 ns(say this is design 2). What is the speedup we can get by using design 2 over design 1 for executing 20 instructions ?

Consider a five stage pipeline having stages IF,ID,OF,EX and WB having stage delays 5,6,14,20 and 8 ns. Buffer delay is 2 ns.(say this is pipeline design 1).Now in this d...

Vivek Jain

1.3k views

Vivek Jain asked Feb 13, 2017

1 votes

1 answer

346

Test by Bikram | Mock GATE | Test 3 | Question: 44
A CPU manufacturer has two designs $P1$ and $P2$ for a synchronous pipeline processor. $P1$ has $5$ pipeline stages with execution times of $3$ $ns$, $4$ $ns$, $3$ $ns$, $2$ $ns$, $4$ $ns$ respectively. The design $P2$ ... time of $3 ns$ each. The time that can be saved by $P2$ over $P1$ to execute $1000$ instructions is ______ $ns$.

A CPU manufacturer has two designs $P1$ and $P2$ for a synchronous pipeline processor.$P1$ has $5$ pipeline stages with execution times of $3$ $ns$, $4$ $ns$, $3$ $ns$, $...

Bikram

262 views

Bikram asked Feb 9, 2017

1 votes

1 answer

347

Mock Test
The answer given is D) Why is option 3 and 4 correct ? In 4) if there is a branch instruction , it can lead to stalls ,so how will it improve the execution ?

The answer given is D) Why is option 3 and 4 correct ?In 4) if there is a branch instruction , it can lead to stalls ,so how will it improve the execution ?

Harsh181996

325 views

Harsh181996 asked Feb 5, 2017

5 votes

1 answer

348

COA pipeline doubt
I) In a 4 stage pipeline processor, if each stage takes 4 cycles then what is CPI in case of successfull pipeline??? II) In a 4 stage pipeline processor, if each stage takes 2,3,4,5 cycles respectively then what is CPI in case ... are branch imstructions and branch address is available in 3rd stage then what should be branch pelanty??(In both the implementations mentioned above)

I) In a 4 stage pipeline processor, if each stage takes 4 cycles then what is CPI in case of successfull pipeline???II) In a 4 stage pipeline processor, if each stage tak...

Rahul Jain25

946 views

Rahul Jain25 asked Feb 5, 2017

1 votes

1 answer

349

Pipeline
The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resolved by operand forwarding techniques. Load instruction output present in 4th stage ALU instruction output ... What is the number of instructions must be inserted to achieve CPI = 1 by using operand forwarding.

The following sequence of instruction is executed in a basic 5 stage pipelined processor (S1, S2, S3, S4, S5). Assume that data dependency present in the program is resol...

srestha

1.7k views

srestha asked Feb 4, 2017

2 votes

3 answers

350

Pipeline: Calculate average instruction execution time
An instruction pipeline has five stages with stage latencies 1 ns, 2ns, 5 ns, 2ns, and 0.5 ns, respectively. A program has 10% branch instructions which execute in the fourth stage and produce the next instruction pointer at the end of the fourth stage. Calculate the average instruction execution time:

An instruction pipeline has five stages with stage latencies 1 ns, 2ns, 5 ns, 2ns, and 0.5 ns, respectively. A program has 10% branch instructions which execute in the fo...

sh!va

6.0k views

sh!va asked Jan 30, 2017

13 votes

0 answers

351

Doubts in PIpelining
1. In case of no data forwarding can we use split phase. 2. Should we have to consider data forwarding, According to options? 3. Where we can use split phase??( I know about WB-ID and EX-ID) @Pc @Arjun Sir Please answer..

1. In case of no data forwarding can we use split phase.2. Should we have to consider data forwarding, According to options?3. Where we can use split phase??( I know abou...

vaishali jhalani

2.4k views

vaishali jhalani asked Jan 30, 2017

1 votes

1 answer

352

Test Series

AmitPatil

513 views

AmitPatil asked Jan 30, 2017

2 votes

2 answers

353

Pipeline : ans should be 13 or 14?
Here loading result should take in ALU ,rt?

Here loading result should take in ALU ,rt?

srestha

889 views

srestha asked Jan 29, 2017

1 votes

2 answers

354

CPI.......
Is CPI of non pipeline processor 6, means non pipeline processor has 6 stages? ----------------------------------------------------------------------------------------------------------------------- ... 4 GHz and an average CPI of 6. System is enhanced to a 8 stage pipelined processor. The clock rate is reduced to 2 GHz in the new processor. Speedup of a pipelined processor is _________.

Is CPI of non pipeline processor 6, means non pipeline processor has 6 stages? -Consider a non-pipeline system has a clock rate 4 GHz and an average CPI of...

srestha

839 views

srestha asked Jan 28, 2017

0 votes

0 answers

355

madeeasy
How are the delay registers to be considered?

How are the delay registers to be considered?

sidsunny

232 views

sidsunny asked Jan 26, 2017

1 votes

1 answer

356

pipeline bypassing
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO ... number of clock cycles needed to execute the following sequence of instruction where operand forwarding from WO to PO and PO to OF is used

A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, O...

Pankaj Joshi

2.2k views

Pankaj Joshi asked Jan 25, 2017

3 votes

1 answer

357

MadeEasy Subject Test: CO & Architecture - Pipelining

Kai

447 views

Kai asked Jan 24, 2017

1 votes

2 answers

358

Data Hazards [GateBook]

biranchi

2.1k views

biranchi asked Jan 24, 2017

5 votes

2 answers

359

MadeEasy CBT 2017: CO & Architecture - Pipelining

Dulqar

1.4k views

Dulqar asked Jan 22, 2017

4 votes

2 answers

360

Pipeline
Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being branch. The value of X such that speedup is atleast 5 is?

Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being b...

Prajwal Bhat

2.0k views

Prajwal Bhat asked Jan 22, 2017

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