Recent questions tagged pipelining / GATE Overflow for GATE CSE

My approach isthere are 40% data access instructions, miss rate is 2%. when miss occurs CPI is 26 (as miss penalty is 25 clocks). when miss doesnt occur CPI is 2. remaini...

Anusha Motamarri

887 views

Anusha Motamarri asked Nov 26, 2016

1 votes

1 answer

396

Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 24
Consider two pipelines A and B. Pipeline A has $8$ stages with uniform stage delay of $2$ns. Pipeline B has $5$ stages with uniform stage delays of $3$ns. Time saved (in ns) by pipeline A compared to pipeline B to execute $100$ instructions is _____.

Consider two pipelines A and B. Pipeline A has $8$ stages with uniform stage delay of $2$ns. Pipeline B has $5$ stages with uniform stage delays of $3$ns. Time saved (in ...

Bikram

295 views

Bikram asked Nov 25, 2016

3 votes

1 answer

397

Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 16
A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots $85$ % of the time, and can fill the second slot only $20$ % of the time. ... the instructions executed are branch instructions, then the percentage improvement in performance achieved by this optimization is ________%.

A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots $85$ % of the time, and can fill the second slot only $20$ % of the t...

Bikram

1.4k views

Bikram asked Nov 25, 2016

0 votes

2 answers

398

Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 13
A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns. The speed-up rotation of the pipeline for $10$ tasks will be _______.

A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns.The speed-up rotation of the p...

Bikram

349 views

Bikram asked Nov 25, 2016

1 votes

1 answer

399

Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 2
In a seven-segment pipeline, each segment takes $1$ cycle. Assuming there are no stalls, the number of clock cycles required to process $180$ tasks in a seven – segment pipeline is _______ cycles.

In a seven-segment pipeline, each segment takes $1$ cycle. Assuming there are no stalls, the number of clock cycles required to process $180$ tasks in a seven – segment...

Bikram

386 views

Bikram asked Nov 25, 2016

1 votes

0 answers

400

Self Made
In pipelining, what is the need of interstate buffer? We are anyway setting the clock equal to the longest delay. The output of one stage will not come out untill the end of one clock cycle. So why do we need the buffer?

In pipelining, what is the need of interstate buffer?We are anyway setting the clock equal to the longest delay. The output of one stage will not come out untill the end ...

Samujjal Das

414 views

Samujjal Das asked Nov 25, 2016

2 votes

1 answer

401

No of clock cycles
Consider the following sequence of instructions executed on the five-stage pipelined processor: Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?

Consider the following sequence of instructions executed on the five-stage pipelined processor:Assuming there is no forwarding, calculate the number of clock cycles neede...

vaishali jhalani

2.4k views

vaishali jhalani asked Nov 25, 2016

4 votes

2 answers

402

pipeline speedup
You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, 1.5ns, 4ns, 3ns, and 0.5ns, what is the best speedup you can get compared to the original processor? Given answer ... / 4ns = 2.5x Speedup In the given answer ,CPI=1.4 is not considered for CTold...That i am not able to understand.

You are given a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4.If a pipelined processor having 5 stages are 1ns, 1.5ns, 4ns, 3ns, an...

vaishali jhalani

4.7k views

vaishali jhalani asked Nov 25, 2016

3 votes

1 answer

403

seedup due to pipelining

vaishali jhalani

592 views

vaishali jhalani asked Nov 24, 2016

2 votes

2 answers

404

What is WAW , WAR and RAW in data hazards please tell
What is WAW , WAR and RAW in data hazard

What is WAW , WAR and RAW in data hazard

LavTheRawkstar

3.6k views

LavTheRawkstar asked Nov 23, 2016

2 votes

2 answers

405

Pipelining and CPI
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. If each pipeline stage adds extra 20ps due to register setup delay. The pipeline stalls 20% of the time for 1 cycle and 5% of the time for 2 cycles (these occurrences are disjoint). What is the new CPI?

Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. If each pipeline stage adds extra 20ps due to register setup delay. The p...

biranchi

2.6k views

biranchi asked Nov 17, 2016

1 votes

1 answer

406

MadeEasy Test Series: CO & Architecture - Pipelining

KISHALAY DAS

564 views

KISHALAY DAS asked Nov 12, 2016

2 votes

3 answers

407

MadeEasy Test Series: CO & Architecture - Pipelining

KISHALAY DAS

500 views

KISHALAY DAS asked Nov 12, 2016

1 votes

1 answer

408

speedup
Consider a machine with 5-stage pipeline with 1ns clock cycle. The second machine with 12-stage pipeline with a 0.6ns clock cycle. The 5-stage pipeline experiences a stall due to data hazard for every 5 instructions, whereas 12 stage pipeline experiences 3 stalls for ... machine is 2 cycles but the second machine is 5 cycles, what is the speed up of 12-stage pipeline over 5 stage pipeline?

Consider a machine with 5-stage pipeline with 1ns clock cycle. The second machine with 12-stage pipeline with a 0.6ns clock cycle. The 5-stage pipeline experiences a stal...

Akriti sood

1.3k views

Akriti sood asked Nov 8, 2016

6 votes

1 answer

409

speedup
Assume we have a computer where the cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache.The only data accesses are loads and stores, and these total 50% of the instructions. If the miss penalty is 25 clock cycles and the miss rate is 2%, how much faster would the computer be if all instructions were cache hits? 1.5 0.7 2.75 1.75

Assume we have a computer where the cycles per instruction (CPI) is 1.0 when all memory accesses hit in the cache.The only data accesses are loads and stores, and these t...

Akriti sood

6.0k views

Akriti sood asked Nov 8, 2016

–4 votes

0 answers

410

COA Interface
What is this RS – 232 interface . Somebody please explain in easy words please

What is this RS – 232 interface . Somebody please explain in easy words please

LavTheRawkstar

853 views

LavTheRawkstar asked Nov 3, 2016

1 votes

1 answer

411

total cycle time in non-pipeline
a) Pipeline contains 5 stages: IF, ID, EX, M and W; b) Each stage requires one clock cycle; c) All memory references hit in cache; d) Following program segment should be processed: // ADD TWO INTEGER ARRAYS LW R4 # 400 L1: LW R1, ... ; Loop if (R4) != 0 Calculate how many clock cycles will take execution of this segment on the regular (non pipelined) architecture ?

a) Pipeline contains 5 stages: IF, ID, EX, M and W;b) Each stage requires one clock cycle;c) All memory references hit in cache;d) Following program segment should be pro...

Akriti sood

2.4k views

Akriti sood asked Nov 3, 2016

1 votes

1 answer

412

conditional and unconditional branch
can someone explain the diff between conditional and unconitional branch with some pipeline diagram or example??

can someone explain the diff between conditional and unconitional branch with some pipeline diagram or example??

Akriti sood

9.7k views

Akriti sood asked Nov 3, 2016

1 votes

1 answer

413

What is happening in the following stages of pipeline ?
What is happening in fetch stage decode stage of pipeline . Please explain in details .

What is happening in fetch stage decode stageof pipeline . Please explain in details .

PEKKA

427 views

PEKKA asked Nov 2, 2016

1 votes

1 answer

414

no data forwarding
Consider the following sequence of instructions executed on the five-stage pipelined processor: I1: lw $1, 40($6) I2: add $2, $3, $1 I3: add $1, $2, $6 I4: sw $2, 20($4) I5 : and $1, $1, $4 Assuming there is no forwarding, calculate the number of clock cycles needed to execute above program ?

Consider the following sequence of instructions executed on the five-stage pipelined processor:I1: lw $1, 40($6)I2: add $2, $3, $1I3: add $1, $2, $6I4: sw $2, 20($4)I5 : ...

Akriti sood

824 views

Akriti sood asked Nov 1, 2016

5 votes

1 answer

415

speedup pipeline
The speedup of a pipeline is 5 and operating with an efficiency of 60% what will be the number of stages ? 8 7 9 1

The speedup of a pipeline is 5 and operating with an efficiency of 60% what will be the number of stages ? 8 7 9 1

Akriti sood

1.7k views

Akriti sood asked Nov 1, 2016

3 votes

1 answer

416

speedup
Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is______________? in this question,speed up is 10/2 = 5 but why it is'nt ... 1.4 * 10) /2 =7.. //i am just confused because speedup is (total time in non pipleine /total time in pipeline)

Consider a non-pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 s...

Akriti sood

783 views

Akriti sood asked Nov 1, 2016

2 votes

1 answer

417

Explain the validity
Explain the validity of the statement Only one clock cycle time is required to execute one insstruction in pipelined processor even if CPI is not 1

Explain the validity of the statement Only one clock cycle time is required to execute one insstruction in pipelined processor even if CPI is not 1

PEKKA

331 views

PEKKA asked Nov 1, 2016

2 votes

2 answers

418

Instruction pipeline utilization factor

Rakesh K

779 views

Rakesh K asked Oct 31, 2016

12 votes

1 answer

419

Advanced Computer Architecture , KAI HWANG | How to Find MAL from Collision Vector | Non-Linear Pipeline

Collition Vector : 1011010 MAL for the above Collition Vector is _____Please also tell me how to calculate efficiency and throughtput

PEKKA

14.9k views

PEKKA asked Oct 27, 2016

4 votes

1 answer

420

Pipeline Efficiency
Will it be 6 or 7?

Will it be 6 or 7?

KISHALAY DAS

4.3k views

KISHALAY DAS asked Oct 21, 2016

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