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Pipelining Explained
Recent questions tagged pipelining
2
votes
3
answers
481
explain
Sourabh Kumar
987
views
Sourabh Kumar
asked
Jun 28, 2015
CO and Architecture
stall
pipelining
+
–
2
votes
1
answer
482
pipelining
Sourabh Kumar
3.3k
views
Sourabh Kumar
asked
Jun 27, 2015
CO and Architecture
pipelining
+
–
1
votes
1
answer
483
In Operand Forwarding technique how does the next instruction is able to access the dependent operand which is calculated in the previous instruction in the same Cpu Cycle?
Anurag_s
1.5k
views
Anurag_s
asked
Apr 3, 2015
CO and Architecture
pipelining
data-dependency
+
–
70
votes
5
answers
484
GATE CSE 2015 Set 3 | Question: 51
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$.$$\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline...
go_editor
40.8k
views
go_editor
asked
Feb 16, 2015
CO and Architecture
gatecse-2015-set3
co-and-architecture
pipelining
difficult
numerical-answers
+
–
46
votes
3
answers
485
GATE CSE 2015 Set 3 | Question: 47
Consider the following code sequence having five instructions from $I_1 \text{ to } I_5$. Each of these instructions has the following format. OP Ri, Rj, Rk Where operation OP is performed on contents of registers Rj and Rk and the result is stored in ... statements is/are correct? Only S1 is true Only S2 is true Only S1 and S3 are true Only S2 and S3 are true
Consider the following code sequence having five instructions from $I_1 \text{ to } I_5$. Each of these instructions has the following format. OP Ri, Rj, RkWhere operatio...
go_editor
21.8k
views
go_editor
asked
Feb 15, 2015
CO and Architecture
gatecse-2015-set3
co-and-architecture
pipelining
data-dependency
normal
+
–
55
votes
5
answers
486
GATE CSE 2015 Set 1 | Question: 38
Consider a non-pipelined processor with a clock rate of $2.5$ gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processor with five stages; but due to the internal pipeline delay, ... $2$ gigahertz. Assume that there are no stalls in the pipeline. The speedup achieved in this pipelined processor is_______________.
Consider a non-pipelined processor with a clock rate of $2.5$ gigahertz and average cycles per instruction of four. The same processor is upgraded to a pipelined processo...
makhdoom ghaya
29.7k
views
makhdoom ghaya
asked
Feb 13, 2015
CO and Architecture
gatecse-2015-set1
co-and-architecture
pipelining
normal
numerical-answers
+
–
81
votes
4
answers
487
GATE CSE 2015 Set 2 | Question: 44
Consider the sequence of machine instruction given below: ... forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instruction is _________.
Consider the sequence of machine instruction given below:$$\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7,...
go_editor
26.2k
views
go_editor
asked
Feb 12, 2015
CO and Architecture
gatecse-2015-set2
co-and-architecture
pipelining
normal
numerical-answers
+
–
3
votes
3
answers
488
Data hazards: RAW,WAR,WAW
Indicate the type of data hazards (RAW, WAR, and WAW) that exist between the following instructions: I1:ADD R1, R2, R3 ; R1 = R2 + R3 I2:ADD R4, R1, R4 ; R4 = R1 + R4 I3:ADD R3, R1, R2 ; R3 = R1 + R2 I4:ADD R1, R1, R4 ; R1 = R1 + ... single instruction?(as in I2 and I4) ii)Do we have to consider only consecutive instructions? (as in I1 and I2) or can it be (I1 and I3) too?
Indicate the type of data hazards (RAW, WAR, and WAW) that exist between the following instructions:I1:ADD R1, R2, R3 ; R1 = R2 + R3I2:ADD R4, R1, R4 ; R4 =...
Keith Kr
2.0k
views
Keith Kr
asked
Dec 16, 2014
CO and Architecture
data-hazards
pipelining
+
–
21
votes
3
answers
489
GATE IT 2005 | Question: 44
We have two designs $D1$ and $D2$ for a synchronous pipeline processor. $D1$ has $5$ pipeline stages with execution times of $3$ nsec, $2$ nsec, $4$ nsec, $2$ nsec and $3$ nsec while the design $D2$ has $8$ pipeline stages each with $2$ nsec ... can be saved using design $D2$ over design $D1$ for executing $100$ instructions? $214$ nsec $202$ nsec $86$ nsec $-200$ nsec
We have two designs $D1$ and $D2$ for a synchronous pipeline processor. $D1$ has $5$ pipeline stages with execution times of $3$ nsec, $2$ nsec, $4$ nsec, $2$ nsec and $3...
Ishrat Jahan
8.1k
views
Ishrat Jahan
asked
Nov 3, 2014
CO and Architecture
gateit-2005
co-and-architecture
pipelining
normal
+
–
37
votes
3
answers
490
GATE IT 2004 | Question: 47
Consider a pipeline processor with $4$ stages $S1$ to $S4$. We want to execute the following loop: for (i = 1; i < = 1000; i++) {I1, I2, I3, I4} where the time taken (in ns) by instructions $I1$ to $I4$ for stages $S1$ to $S4$ ... output of $I1$ for $i = 2$ will be available after $\text{11 ns}$ $\text{12 ns}$ $\text{13 ns}$ $\text{28 ns}$
Consider a pipeline processor with $4$ stages $S1$ to $S4$. We want to execute the following loop:for (i = 1; i < = 1000; i++) {I1, I2, I3, I4}where the time taken (in ns...
Ishrat Jahan
12.3k
views
Ishrat Jahan
asked
Nov 2, 2014
CO and Architecture
gateit-2004
co-and-architecture
pipelining
normal
+
–
45
votes
5
answers
491
GATE IT 2006 | Question: 79
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX ... is used. The number of clock cycles required to complete the sequence of instructions is $10$ $12$ $14$ $16$
A pipelined processor uses a 4-stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The...
Ishrat Jahan
17.2k
views
Ishrat Jahan
asked
Nov 1, 2014
CO and Architecture
gateit-2006
co-and-architecture
pipelining
normal
+
–
46
votes
2
answers
492
GATE IT 2006 | Question: 78
A pipelined processor uses a $4-$stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). The arithmetic operations as well as the load and store operations are carried out in the EX stage. The sequence of ... sequence of instructions are, respectively, $2, 2, 4$ $3, 2, 3$ $4, 2, 2$ $3, 3, 2$
A pipelined processor uses a $4-$stage instruction pipeline with the following stages: Instruction fetch (IF), Instruction decode (ID), Execute (EX) and Writeback (WB). T...
Ishrat Jahan
15.3k
views
Ishrat Jahan
asked
Nov 1, 2014
CO and Architecture
gateit-2006
co-and-architecture
pipelining
normal
+
–
41
votes
6
answers
493
GATE IT 2007 | Question: 6, ISRO2011-25
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycles respectively. What is the asymptotic speedup assuming that a very large number of instructions are to be executed? $1.83$ $2$ $3$ $6$
A processor takes $12$ cycles to complete an instruction I. The corresponding pipelined processor uses $6$ stages with the execution times of $3, 2, 5, 4, 6$ and $2$ cycl...
Ishrat Jahan
13.2k
views
Ishrat Jahan
asked
Oct 29, 2014
CO and Architecture
gateit-2007
co-and-architecture
pipelining
normal
isro2011
+
–
42
votes
4
answers
494
GATE IT 2008 | Question: 40
A non pipelined single cycle processor operating at $100\;\text{MHz}$ is converted into a synchronous pipelined processor with five stages requiring $2.5\;\text{nsec}, 1.5\;\text{nsec}, 2\;\text{nsec}, 1.5\;\text{nsec}$ and $2.5\;\text{nsec}$, respectively ... $4.5$ $4.0$ $3.33$ $3.0$
A non pipelined single cycle processor operating at $100\;\text{MHz}$ is converted into a synchronous pipelined processor with five stages requiring $2.5\;\text{nsec}, ...
Ishrat Jahan
13.6k
views
Ishrat Jahan
asked
Oct 28, 2014
CO and Architecture
gateit-2008
co-and-architecture
pipelining
normal
+
–
47
votes
3
answers
495
GATE CSE 2010 | Question: 33
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ... $13$ $15$ $17$ $19$
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID,...
go_editor
21.8k
views
go_editor
asked
Sep 29, 2014
CO and Architecture
gatecse-2010
co-and-architecture
pipelining
normal
+
–
42
votes
2
answers
496
GATE CSE 2011 | Question: 41
Consider an instruction pipeline with four stages $\text{(S1, S2, S3 and S4)}$ each with combinational circuit only. The pipeline registers are required between each stage and at the end of the last stage. Delays for the stages and for the pipeline ... under ideal conditions when compared to the corresponding non-pipeline implementation? $4.0$ $2.5$ $1.1$ $3.0$
Consider an instruction pipeline with four stages $\text{(S1, S2, S3 and S4)}$ each with combinational circuit only. The pipeline registers are required between each stag...
go_editor
13.5k
views
go_editor
asked
Sep 29, 2014
CO and Architecture
gatecse-2011
co-and-architecture
pipelining
normal
+
–
53
votes
7
answers
497
GATE CSE 2014 Set 3 | Question: 43
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), and register writeback (WB) with stage latencies $1$ ns, $2.2 $ ns, $2$ ... program on the old and the new design are $P$ and $Q$ nanoseconds, respectively. The value of $P/Q$ is __________.
An instruction pipeline has five stages, namely, instruction fetch (IF), instruction decode and register fetch (ID/RF), instruction execution (EX), memory access (MEM), a...
go_editor
22.0k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set3
co-and-architecture
pipelining
numerical-answers
normal
+
–
31
votes
4
answers
498
GATE CSE 2014 Set 3 | Question: 9
Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. $\text{P1:}$ Four-stage pipeline with stage latencies $\text{1 ns, 2 ns, 2 ns, 1 ns}$. $\text{P2:}$ Four-stage pipeline with stage latencies ... $\text{P1}$ $\text{P2}$ $\text{P3}$ $\text{P4}$
Consider the following processors (ns stands for nanoseconds). Assume that the pipeline registers have zero latency. $\text{P1:}$ Four-stage pipeline with stage latencies...
go_editor
8.2k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set3
co-and-architecture
pipelining
normal
+
–
50
votes
9
answers
499
GATE CSE 2014 Set 1 | Question: 43
Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is executing on this $6$-stage pipeline, the speedup achieved with respect to non-pipelined execution if $25$% of the instructions incur $2$ pipeline stall cycles is ____________
Consider a $6$-stage instruction pipeline, where all stages are perfectly balanced. Assume that there is no cycle-time overhead of pipelining. When an application is exec...
go_editor
19.8k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set1
co-and-architecture
pipelining
numerical-answers
normal
+
–
50
votes
9
answers
500
GATE CSE 2006 | Question: 42
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new ... : $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the...
Rucha Shelke
20.9k
views
Rucha Shelke
asked
Sep 26, 2014
CO and Architecture
gatecse-2006
co-and-architecture
pipelining
normal
+
–
34
votes
3
answers
501
GATE CSE 1999 | Question: 13
An instruction pipeline consists of $4$ stages - Fetch $(F)$, Decode field $(D)$, Execute $(E)$ and Result Write $(W)$. The $5$ instructions in a certain instruction sequence need these stages for the different number of clock cycles as shown by the ... $5$ instructions.
An instruction pipeline consists of $4$ stages – Fetch $(F)$, Decode field $(D)$, Execute $(E)$ and Result Write $(W)$. The $5$ instructions in a certain instruction se...
Kathleen
10.4k
views
Kathleen
asked
Sep 23, 2014
CO and Architecture
gate1999
co-and-architecture
pipelining
normal
numerical-answers
+
–
142
votes
4
answers
502
GATE CSE 2005 | Question: 68
A $5$ stage pipelined CPU has the following sequence of stages: IF - instruction fetch from instruction memory RD - Instruction decode and register read EX - Execute: ALU operation for data and address computation MA - Data memory access - for write access, the ... taken to complete the above sequence of instructions starting from the fetch of $I_1$? $8$ $10$ $12$ $15$
A $5$ stage pipelined CPU has the following sequence of stages:IF – instruction fetch from instruction memoryRD – Instruction decode and register readEX – Execute: ...
Kathleen
45.8k
views
Kathleen
asked
Sep 22, 2014
CO and Architecture
gatecse-2005
co-and-architecture
pipelining
normal
+
–
52
votes
10
answers
503
GATE CSE 2009 | Question: 28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ ... the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} $16$ $23$ $28$ $30$
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below:$$\begin{array}{|...
Kathleen
33.9k
views
Kathleen
asked
Sep 22, 2014
CO and Architecture
gatecse-2009
co-and-architecture
pipelining
normal
+
–
32
votes
4
answers
504
GATE CSE 2007 | Question: 37, ISRO2009-37
Consider a pipelined processor with the following four stages: IF: Instruction Fetch ID: Instruction Decode and Operand Fetch EX: Execute WB: Write Back The IF, ID and WB stages take one clock cycle each to complete the operation. The number of clock cycles for the EX ... $ R5$-$R4} \\ \end{array}$ $7$ $8$ $10$ $14$
Consider a pipelined processor with the following four stages:IF: Instruction FetchID: Instruction Decode and Operand FetchEX: ExecuteWB: Write BackThe IF, ID and WB stag...
Kathleen
15.8k
views
Kathleen
asked
Sep 21, 2014
CO and Architecture
gatecse-2007
co-and-architecture
pipelining
normal
isro2009
+
–
35
votes
3
answers
505
GATE CSE 2004 | Question: 69
A 4-stage pipeline has the stage delays as $150$, $120$, $160$ and $140$ $nanoseconds$, respectively. Registers that are used between the stages have a delay of $5$ $nanoseconds$ ... be: $\text{120.4 microseconds}$ $\text{160.5 microseconds}$ $\text{165.5 microseconds}$ $\text{590.0 microseconds}$
A 4-stage pipeline has the stage delays as $150$, $120$, $160$ and $140$ $nanoseconds$, respectively. Registers that are used between the stages have a delay of $5$ $nano...
Kathleen
20.3k
views
Kathleen
asked
Sep 18, 2014
CO and Architecture
gatecse-2004
co-and-architecture
pipelining
normal
+
–
30
votes
5
answers
506
GATE CSE 2003 | Question: 10, ISRO-DEC2017-41
For a pipelined CPU with a single ALU, consider the following situations The ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operand The execution of a conditional jump instruction The $j^{th}$ and ${j+1}^{st}$ ... ALU at the same time. Which of the above can cause a hazard I and II only II and III only III only All the three
For a pipelined CPU with a single ALU, consider the following situationsThe ${j+1}^{st}$ instruction uses the result of the $j^{th}$ instruction as an operandThe executio...
Kathleen
9.4k
views
Kathleen
asked
Sep 16, 2014
CO and Architecture
gatecse-2003
co-and-architecture
pipelining
normal
isrodec2017
+
–
29
votes
3
answers
507
GATE CSE 2002 | Question: 2.6, ISRO2008-19
The performance of a pipelined processor suffers if: the pipeline stages have different delays consecutive instructions are dependent on each other the pipeline stages share hardware resources All of the above
The performance of a pipelined processor suffers if:the pipeline stages have different delaysconsecutive instructions are dependent on each otherthe pipeline stages share...
Kathleen
11.4k
views
Kathleen
asked
Sep 15, 2014
CO and Architecture
gatecse-2002
co-and-architecture
pipelining
easy
isro2008
+
–
54
votes
2
answers
508
GATE CSE 2001 | Question: 12
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle ... Show all data dependencies between the four instructions. Identify the data hazards. Can all hazards be avoided by forwarding in this case.
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or registe...
Kathleen
17.3k
views
Kathleen
asked
Sep 14, 2014
CO and Architecture
gatecse-2001
co-and-architecture
pipelining
normal
descriptive
+
–
71
votes
8
answers
509
GATE CSE 2000 | Question: 12
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the instruction after the branch is not fetched till the branch instruction ... 50% of the conditional branch instructions are such that the branch is taken, calculate the average instruction execution time.
An instruction pipeline has five stages where each stage take 2 nanoseconds and all instruction use all five stages. Branch instructions are not overlapped. i.e., the ins...
Kathleen
17.3k
views
Kathleen
asked
Sep 14, 2014
CO and Architecture
gatecse-2000
co-and-architecture
pipelining
normal
descriptive
+
–
35
votes
4
answers
510
GATE CSE 2000 | Question: 1.8
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say that T1 ≤ T2 T1 ≥ T2 T1 < T2 T1 and T2 plus the time taken for one instruction fetch cycle
Comparing the time T1 taken for a single instruction on a pipelined CPU with time T2 taken on a non-pipelined but identical CPU, we can say thatT1 ≤ T2T1 ≥ T2T1 < T2T...
Kathleen
11.4k
views
Kathleen
asked
Sep 14, 2014
CO and Architecture
gatecse-2000
pipelining
co-and-architecture
easy
+
–
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