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Pipelining Explained
Recent questions tagged pipelining
0
votes
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61
#Exam
Pipe line consists of 5 stages , add instruction takes 2 cycles in EX stage, mul instruction takes 3 cycles in EX stage .. If we don't use buffer in between stages(no store and forward) , what is the time taken to execute two instruction add,mul???
Pipe line consists of 5 stages , add instruction takes 2 cycles in EX stage, mul instruction takes 3 cycles in EX stage .. If we don't use buffer in between stages(no sto...
RamaSivaSubrahmanyam
430
views
RamaSivaSubrahmanyam
asked
Sep 14, 2022
CO and Architecture
co-and-architecture
pipelining
instruction-execution
numerical-answers
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0
votes
0
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62
#pipelining self-doubt
In pipielining add instruction takes 2 cycles in execution stage and mul instruction takes 4 clock cycles in the execution stage and in the remaining stages each instruction takes 1 cycle ... Now if we execute both instruction parlelly in pipelining , we get 2 stalls .. Now the question is , how do we treat those stalls? That means are they hazards or simply stalls??
In pipielining add instruction takes 2 cycles in execution stage and mul instruction takes 4 clock cycles in the execution stage and in the remaining stages each instruct...
RamaSivaSubrahmanyam
242
views
RamaSivaSubrahmanyam
asked
Sep 12, 2022
CO and Architecture
co-and-architecture
pipelining
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0
votes
1
answer
63
Applied Gate Test Series
lalitver10
357
views
lalitver10
asked
Sep 10, 2022
CO and Architecture
pipelining
co-and-architecture
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–
1
votes
0
answers
64
Computer organization and architecture
1. In memory hierarchy the fattest memory type is cache memory next to register. So describe mapping process(transformation data from memory to cache memory)
1. In memory hierarchy the fattest memory type is cache memory next to register. So describe mapping process(transformation data from memory to cache memory)
kidussss
306
views
kidussss
asked
Sep 1, 2022
CO and Architecture
co-and-architecture
pipelining
control-unit
ieee-representation
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0
votes
0
answers
65
Computer organization and architecture
1. Assume to transfer serial data we use shift register. So if we need to transfer 8 bit data to 8 bit shifter register: a) Show the content of shift register after 2 bit transferred using diagram? b) Show the overall serial transfer of all data using diagram. c) Determine how many shifting is performed to transfer all data?
1. Assume to transfer serial data we use shift register. So if we need to transfer 8 bit data to 8 bit shifter register:a) Show the content of shift register after 2 bit ...
kidussss
207
views
kidussss
asked
Sep 1, 2022
CO and Architecture
co-and-architecture
pipelining
control-unit
ieee-representation
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5
votes
1
answer
66
GO Classes Test Series 2023 | CO and Architecture | Test 2 | Question: 8
Consider the following instruction sequence: ... , then which of the following is true? $\mathrm{B}=4$ $\mathrm{A}=4$ $\mathrm{A}=2$ $\mathrm{C}=2$
Consider the following instruction sequence:$$\begin{aligned}&\text{I}_1: \text{R}_1=100\\&\text{I}_2: \text{R}_1=\text{R}_2+\text{R}_4\\&\text{I}_3: \text{R}_2=\text{R}_...
GO Classes
485
views
GO Classes
asked
Aug 31, 2022
CO and Architecture
goclasses2024-coa-2-weekly-quiz
goclasses
co-and-architecture
pipelining
data-dependency
multiple-selects
2-marks
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–
0
votes
0
answers
67
Best Open Video Playlist for Instruction Pipelining Topic | CO & A
Please list out the best free available video playlist for Instruction Pipelining from CO & A as an answer here (only one playlist per answer). We'll then select the best playlist and add to GO classroom video ... standard ones are more likely to be selected as best. For the full list of selected videos please see here
Please list out the best free available video playlist for Instruction Pipelining from CO & A as an answer here (only one playlist per answer). We'll then select the best...
makhdoom ghaya
193
views
makhdoom ghaya
asked
Aug 16, 2022
Study Resources
go-classroom
missing-videos
free-videos
video-links
instruction
pipelining
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0
votes
1
answer
68
In a pipelined architecture Static branch prediction is used with branch taken assumption. Assume that 30% of the instructions executed for a program are branch instructions. Each stage has 2 nsec delay. Average Execution time(in nsec) if 80 % of the instructions are taken?
In a pipelined architecture Static branch prediction is used with branch taken assumption. Assume that 30% of the instructions executed for a program are branch instructi...
kathan Mistry
613
views
kathan Mistry
asked
Aug 9, 2022
CO and Architecture
co-and-architecture
pipelining
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0
votes
1
answer
69
Question on Pipelining
In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If 70% of the conditional branches are taken, calculate % loss of speed-up due to branch instructions. It is very difficult to understand this question and solve it. Please help.
In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If ...
Swarnava Bose
1.1k
views
Swarnava Bose
asked
Jul 2, 2022
CO and Architecture
co-and-architecture
pipelining
speedup
branch-conditional-instructions
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–
0
votes
1
answer
70
Pipeline Architecture
if an unpipelined processor with a cycle time of 25 ns is evenly divided into 5 pipeline stages using pipeline latches with 1-ns latency,what is the total latency of the pipeline? how about if the processor is divided into 50 pipeline stages?
if an unpipelined processor with a cycle time of 25 ns is evenly divided into 5 pipeline stages using pipeline latches with 1-ns latency,what is the total latency of the ...
shima abdullah
876
views
shima abdullah
asked
Jun 27, 2022
CO and Architecture
co-and-architecture
pipelining
+
–
18
votes
5
answers
71
GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ ...
Arjun
10.1k
views
Arjun
asked
Feb 15, 2022
CO and Architecture
gatecse-2022
numerical-answers
co-and-architecture
pipelining
stall
2-marks
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–
4
votes
0
answers
72
#pipeline #self doubt
Consider a 5—stage pipeline processor used to execute 200 number of instructions and among those 100 instructions cause 3 stall cycles each. What is the total cycles required for these operation if CPI is not equal to one.
Consider a 5—stage pipeline processor used to execute 200 number of instructions and among those 100 instructions cause 3 stall cycles each. What is the total cycles re...
jayadev
393
views
jayadev
asked
Feb 3, 2022
CO and Architecture
co-and-architecture
pipelining
stall
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–
3
votes
1
answer
73
GATE Overflow Test Series | Mock GATE | Test 6 | Question: 38
Consider a $5$-stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (Memory), and WB (Write Back). All register reads take place in the second phase of a clock cycle and all register ... after read) hazards by $B$ and WAW (Write after write) hazards by $C,$ then $2A+3B+C =$ ___________
Consider a $5$-stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (Memory), and WB (Write Back). All register reads tak...
Arjun
344
views
Arjun
asked
Jan 30, 2022
CO and Architecture
go2025-mockgate-6
numerical-answers
co-and-architecture
pipelining
2-marks
+
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