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Recent questions tagged registers
1
votes
1
answer
1
unacademy test series
please explain this question
please explain this question
lovish_bhatia
167
views
lovish_bhatia
asked
Dec 13, 2023
CO and Architecture
co-and-architecture
registers
unacademy-test-series
+
–
0
votes
2
answers
2
Arihant Gate Tutor
If a processor has 32-bit virtual address, 28-bit physical address, 2 kb pages. How many bits are required for the virtual, physical page number? 17, 21 21, 17 6, 10 None The answer given is b. 21, 17
If a processor has 32-bit virtual address, 28-bit physical address, 2 kb pages. How many bits are required for the virtual, physical page number?17, 2121, 176, 10NoneThe ...
arkaprava_gupta
1.5k
views
arkaprava_gupta
asked
Dec 23, 2022
CO and Architecture
co-and-architecture
virtual-memory
operating-system
registers
+
–
0
votes
1
answer
3
Arihant Gate Tutor
Which of the following processor registers are used for fetch and execute operations ? Program Counter Instruction Register Address Register Options : a and b b and c a and c None of these
Which of the following processor registers are used for fetch and execute operations ?Program CounterInstruction RegisterAddress RegisterOptions :a and bb and ca and cNon...
arkaprava_gupta
334
views
arkaprava_gupta
asked
Dec 23, 2022
CO and Architecture
co-and-architecture
registers
microprocessors
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–
0
votes
0
answers
4
College papers
A general register organization has 32 registers with 20 bits in each, an ALU and a destination decoder then formulate a control word for the system assuming that the ALU has 74 operations.
A general register organization has 32 registers with 20 bits in each, an ALU and a destination decoder then formulate a control word for the system assuming that the ALU...
AadityaMishra112245
270
views
AadityaMishra112245
asked
Nov 16, 2021
CO and Architecture
co-and-architecture
registers
+
–
0
votes
0
answers
5
Bits HD 2019
In a microprocessor, size of register is generally: Lesser than the size of the data it operates on Greater than the size of the data it operates on Equal to the size of the data it operates on
In a microprocessor, size of register is generally:Lesser than the size of the data it operates onGreater than the size of the data it operates onEqual to the size of th...
manikgupta123
900
views
manikgupta123
asked
May 29, 2019
CO and Architecture
bits
bits-hd
co-and-architecture
microprocessors
registers
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–
0
votes
0
answers
6
Morris Mano Edition 3 Exercise 7 Question 12 (Page No. 304)
It was stated that the 2's complement of a binary number can be formed by lowing all the least significant 0's and the first 1 unchanged and complementing all the other higher significant bits, Design a serial 2's complementer using this procedure. The ... the unchanged bits($ x \oplus 0 = x$) or complement the bits ($ x \oplus 1 = x'$).
It was stated that the 2’s complement of a binary number can be formed by lowing all the least significant 0’s and the first 1 unchanged and complementing all the oth...
ajaysoni1924
688
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
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–
0
votes
0
answers
7
Morris Mano Edition 3 Exercise 7 Question 11 (Page No. 304)
what changes are needed to the figure to convert it to a serial subtractor that subtracts the content of register B from the content of register A?
what changes are needed to the figure to convert it to a serial subtractor that subtracts the content of register B from the content of register A?
ajaysoni1924
664
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
serial-adder
registers
+
–
2
votes
0
answers
8
Morris Mano Edition 3 Exercise 7 Question 10 (Page No. 304)
The serial adder of the figure uses 4-bit registers. Register A holds binary number 0101 and register B holds 0111. The carry flip-flop is initially set to 0. List the binary values in register A and carry flipflop after each shift.
The serial adder of the figure uses 4-bit registers. Register A holds binary number 0101 and register B holds 0111. The carry flip-flop is initially set to 0. List the b...
ajaysoni1924
951
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
serial-adder
+
–
0
votes
0
answers
9
Morris Mano Edition 3 Exercise 7 Question 9 (Page No. 303)
Draw the logic diagram of a 4-bit register with four D flip-flops and four $4 \times 1$ multiplexer with mode-selection inputs $s _1 and s _0$. The register operates according to the following function table: $s _1$ ... no change 0 1 complement the four output 1 0 clear register to 0 (synchronous with the clock) 1 1 load parallel data
Draw the logic diagram of a 4-bit register with four D flip-flops and four $4 \times 1$ multiplexer with mode-selection inputs $s _1 and s _0$. The register operates acco...
ajaysoni1924
332
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
+
–
0
votes
0
answers
10
Morris Mano Edition 3 Exercise 7 Question 8 (Page No. 303)
Design a shift register with a parallel load that operates according to the following function table: shift load register operation 0 0 no change 0 1 load parallel data 1 x shift right
Design a shift register with a parallel load that operates according to the following function table:shiftloadregister operation00no change01load parallel data1xshift rig...
ajaysoni1924
421
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
+
–
0
votes
0
answers
11
Morris Mano Edition 3 Exercise 7 Question 7 (Page No. 303)
The 4-bit bidirectional shift register with parallel load shown in the figure is enclosed within one IC package. Draw a block diagram of the IC showing all inputs and outputs. Include two pins for power supply. Draw a block diagram using two ICs to produce an 8-bit bidirectional shift register with the parallel load.
The 4-bit bidirectional shift register with parallel load shown in the figure is enclosed within one IC package.Draw a block diagram of the IC showing all inputs and outp...
ajaysoni1924
2.3k
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
+
–
0
votes
0
answers
12
Morris Mano Edition 3 Exercise 7 Question 6 (Page No. 303)
What is the difference between serial and parallel transfer? Explain how to convert serial data to parallel and parallel to serial. what type of registers is needed?
What is the difference between serial and parallel transfer? Explain how to convert serial data to parallel and parallel to serial. what type of registers is needed?
ajaysoni1924
176
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
descriptive
+
–
0
votes
0
answers
13
Morris Mano Edition 3 Exercise 7 Question 5 (Page No. 303)
The content of the 4-bit register initially is 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of reigster after each shift?
The content of the 4-bit register initially is 1101. The register is shifted six times to the right with the serial input being 101101. What is the content of reigster af...
ajaysoni1924
536
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
+
–
3
votes
0
answers
14
Morris Mano Edition 3 Exercise 7 Question 4 (Page No. 303)
Design a sequential circuit of the state diagram given in the figure using a3-bit register and a $16 \times 4$ ROM.
Design a sequential circuit of the state diagram given in the figure using a3-bit register and a $16 \times 4$ ROM.
ajaysoni1924
700
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
registers
+
–
0
votes
0
answers
15
Morris Mano Edition 3 Exercise 7 Question 2,3 (Page No. 303)
Change the asynchronous-clear-circuit of the figure to the synchronous-clear-circuit, The modified register will have parallel load capability and asynchronous clear capability, but no asynchronous clear circuit. The register is cleared ... input CP goes through a negative transition while the D input of all the flip-flops are 0.
Change the asynchronous-clear-circuit of the figure to the synchronous-clear-circuit, The modified register will have parallel load capability and asynchronous clear capa...
ajaysoni1924
950
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
registers
+
–
0
votes
0
answers
16
Morris Mano Edition 3 Exercise 7 Question 1 (Page No. 303)
Include a 2-input NAND gate with the register of the figure and connect the gate output to CP inputs of all the flip-flops. One input of the NAND gate receives input from the clock-pulse-generator. Another input of NAND gate provides parallel load control. Explain the operation of the modified register.
Include a 2-input NAND gate with the register of the figure and connect the gate output to CP inputs of all the flip-flops. One input of the NAND gate receives input from...
ajaysoni1924
549
views
ajaysoni1924
asked
Apr 6, 2019
Digital Logic
digital-logic
morris-mano
sequential-circuit
synchronous-asynchronous-circuits
registers
+
–
0
votes
0
answers
17
adressing modes
For Given machine instructions LW R4 #400 L1:LW R1, 0,(R4) LW R2 400(R4) ADDI R3, R1, R2 SW R3, 0(R4) SUB R4, R4, #4 BNZ R4, L1 on a 5 stage pipeline processor, 1 clock cycle per stage. how mAny clock cycles willtake execution of this segment on the regular architecture?
For Given machine instructionsLW R4 #400L1:LW R1, 0,(R4)LW R2 400(R4)ADDI R3, R1, R2SW R3, 0(R4)SUB R4, R4, #4BNZ R4, L1on a 5 stage pipeline processor, 1 clock cycle per...
rishabhdevsingh1
634
views
rishabhdevsingh1
asked
Nov 10, 2018
CO and Architecture
co-and-architecture
machine-instruction
registers
pipelining
addressing-modes
numerical-answers
+
–
0
votes
1
answer
18
adressing modes
Given 2 machine instructions, LW R4 #400 LW R1, 0,(R4) IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory location operand..I want to clarify whether the value stored in register is same as adress that register points.
Given 2 machine instructions,LW R4 #400LW R1, 0,(R4)IN second instruction what will be loaded in R1,is it the operand at memory location 400?or some random memory locatio...
rishabhdevsingh1
1.2k
views
rishabhdevsingh1
asked
Nov 9, 2018
CO and Architecture
co-and-architecture
machine-instruction
addressing-modes
registers
numerical-answers
+
–
1
votes
1
answer
19
status Register & I/o
What is the work of status register in I/O operation ?
What is the work of status register in I/O operation ?
Sunil8860
1.6k
views
Sunil8860
asked
Aug 8, 2017
CO and Architecture
co-and-architecture
io-handling
registers
+
–
4
votes
3
answers
20
ISRO2008-55
The Memory Address Register is a hardware memory device which denotes the location of the current instruction being executed. is a group of electrical ckt, that performs the intent of instructions fetched from memory contains the address of the memory location that ... location specified by the MAR after a "read" or the new contents of the memory prior to a "write"
The Memory Address Registeris a hardware memory device which denotes the location of the current instruction being executed.is a group of electrical ckt, that performs th...
go_editor
3.3k
views
go_editor
asked
Jun 12, 2016
CO and Architecture
isro2008
co-and-architecture
registers
+
–
6
votes
2
answers
21
ISRO2007-08
A read bit can be read and written by CPU and written by peripheral by peripheral and written by CPU by CPU and written by the peripheral
A read bit can be readand written by CPUand written by peripheralby peripheral and written by CPUby CPU and written by the peripheral
go_editor
4.8k
views
go_editor
asked
Jun 10, 2016
CO and Architecture
isro2007
co-and-architecture
registers
+
–
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