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Recent questions tagged ripple-counter-operation

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Recent questions tagged ripple-counter-operation

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3
Morris Mano Edition 3 Exercise 7 Question 14 (Page No. 304)
Draw the logic diagram of a 4-bit binary ripple down counter using the following. Flip-flops that trigger on the positive edge transition of the clock. Flip-flop that trigger on the negative edge transition of the clock.
Draw the logic diagram of a 4-bit binary ripple down counter using the following. Flip-flops that trigger on the positive edge transition of the clock. Flip-flop that trigger on the negative edge transition of the clock.
asked Apr 6, 2019 in Digital Logic ajaysoni1924 68 views
0 votes
0 answers
4
Digital Logic made easy
Consider the circuit given below: MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and output of comparator was A=B. The clock pulse is applied. Find the minimum no of clock pulses required to make A=B again.
Consider the circuit given below: MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and output of comparator was A=B. The clock pulse is applied. Find the minimum no of clock pulses required to make A=B again.
asked Jan 5, 2019 in Digital Logic Sambhrant Maurya 941 views
5 votes
1 answer
5
GO2019-FLT1-25
Consider the function: int fun(int n) { if (n==4) return n; else return 2*fun(n+1); } A MOD-16 ripple counter is holding the count $(1001)_2.$ What will be the count after "$(\text{fun}(2)+15)_{10}$" clock pulses? $(1000)_2$ $(1010)_2$ $(1011)_2$ $(1101)_2$
Consider the function: int fun(int n) { if (n==4) return n; else return 2*fun(n+1); } A MOD-16 ripple counter is holding the count $(1001)_2.$ What will be the count after "$(\text{fun}(2)+15)_{10}$" clock pulses? $(1000)_2$ $(1010)_2$ $(1011)_2$ $(1101)_2$
asked Dec 27, 2018 in Digital Logic Ruturaj Mohanty 293 views
0 votes
0 answers
6
digital logic
A ripple counter is made with three positive edge triggered flip-flops. If the output of previous lower significant bit flipflop is used as a triggering clock pulse of the next higher significant bit flip-flop, then the resultant counter is a A MOD 3 up counter B ... D MOD 8 down counter since all are positive edge triggered flip flops ,so shouldn't the answer be mod 8 up counter??
A ripple counter is made with three positive edge triggered flip-flops. If the output of previous lower significant bit flipflop is used as a triggering clock pulse of the next higher significant bit flip-flop, then the resultant counter is a A MOD 3 up counter B MOD 3 ... counter D MOD 8 down counter since all are positive edge triggered flip flops ,so shouldn't the answer be mod 8 up counter??
asked Oct 2, 2018 in Digital Logic Gate Fever 243 views
1 vote
2 answers
7
UGCNET-July-2018-II: 94
What does the following logic diagram represent? Synchronous Counter Ripple Counter Combinational Circuit Mod 2 Counter
What does the following logic diagram represent? Synchronous Counter Ripple Counter Combinational Circuit Mod 2 Counter
asked Jul 13, 2018 in Digital Logic Pooja Khatri 1.3k views
3 votes
0 answers
8
MultiSubject (CO, DIgital, DS)
A 4-bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 100 ns, the maximum clock frequency that can be used is equal to: Ans 2.5MHz. I think it should be $\frac{1}{16*10^{-7}} = 0.625MHz$ ... minimum number of comparisons that will be needed in the worst case by the optimal algorithm for doing this is Ans = 840 I am getting 860.
A 4-bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 100 ns, the maximum clock frequency that can be used is equal to: Ans 2.5MHz. I think it should be $\frac{1}{16*10^{-7}} = 0.625MHz$ Consider a system employing ... The minimum number of comparisons that will be needed in the worst case by the optimal algorithm for doing this is Ans = 840 I am getting 860.
asked Jan 25, 2018 in Programming Shubhanshu 593 views
2 votes
1 answer
9
made easy test series
asked Jan 6, 2018 in Digital Logic rohit vishkarma 128 views
0 votes
0 answers
10
Made_Easy_test
Pr0,Pr1,Pr2????
Pr0,Pr1,Pr2????
asked Nov 30, 2017 in Digital Logic hs_yadav 343 views
2 votes
1 answer
11
digital logic 3
in a 6 bit ripple counter, the MOD of UP couting is 14 , the MOD of down counting is........?
in a 6 bit ripple counter, the MOD of UP couting is 14 , the MOD of down counting is........?
asked Sep 23, 2017 in Digital Logic hem chandra joshi 282 views
5 votes
1 answer
13
Digital
An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50 ns. The frequency of the input signal which can be used for proper operation of the counter is approximately ______________
An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50 ns. The frequency of the input signal which can be used for proper operation of the counter is approximately ______________
asked Nov 4, 2016 in Digital Logic srestha 1.4k views
1 vote
1 answer
14
UGCNET-AUG2016-III: 1
A ripple counter is a $(n)$ : Synchronous Counter Asynchronous counter Parallel counter None of the above
A ripple counter is a $(n)$ : Synchronous Counter Asynchronous counter Parallel counter None of the above
asked Sep 30, 2016 in Digital Logic makhdoom ghaya 444 views
1 vote
1 answer
15
UGCNET-Sep2013-III: 36
A binary ripple counter is required to count up to 16383. How many flip-flops are required? 16382 8191 512 14
A binary ripple counter is required to count up to 16383. How many flip-flops are required? 16382 8191 512 14
asked Jul 24, 2016 in Digital Logic jothee 2.1k views
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