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Recent questions tagged ripple-counter-operation

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Made Easy Test Series Question
The output frequency of a decade counter that is clocked from a 50 kHz signal is _________ kHz.

prnv28 asked in Digital Logic Dec 31, 2021

by prnv28

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Morris Mano Edition 3 Exercise 7 Question 19 (Page No. 304)
Design a 4-bit ripple counter with D flip-flops.

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

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Morris Mano Edition 3 Exercise 7 Question 15 (Page No. 304)
Construct a BCD ripple counter using a 4-bit binary ripple counter that can be cleared asynchronously and an external NAND gate.

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

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4

Morris Mano Edition 3 Exercise 7 Question 14 (Page No. 304)
Draw the logic diagram of a 4-bit binary ripple down counter using the following. Flip-flops that trigger on the positive edge transition of the clock. Flip-flop that trigger on the negative edge transition of the clock.

ajaysoni1924 asked in Digital Logic Apr 6, 2019

by ajaysoni1924

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2 votes

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5

Digital Logic made easy
Consider the circuit given below: MSB and LSB of mod 10 ripple counter act as clock to ripple down and up counter respectively. Initially all the counters were cleared and output of comparator was A=B. The clock pulse is applied. Find the minimum no of clock pulses required to make A=B again.

Sambhrant Maurya asked in Digital Logic Jan 5, 2019

by Sambhrant Maurya

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5 votes

2 answers

6

GATE Overflow | Mock GATE | Test 1 | Question: 25
Consider the function: int fun(int n) { if (n==4) return n; else return 2*fun(n+1); } A MOD-16 ripple counter is holding the count $(1001)_2.$ What will be the count after "$(\text{fun}(2)+15)_{10}$" clock pulses? $(1000)_2$ $(1010)_2$ $(1011)_2$ $(1101)_2$

Ruturaj Mohanty asked in Digital Logic Dec 27, 2018

by Ruturaj Mohanty

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digital logic
A ripple counter is made with three positive edge triggered flip-flops. If the output of previous lower significant bit flipflop is used as a triggering clock pulse of the next higher significant bit flip-flop, then the resultant counter is a A MOD 3 up counter B ... D MOD 8 down counter since all are positive edge triggered flip flops ,so shouldn't the answer be mod 8 up counter??

Gate Fever asked in Digital Logic Oct 2, 2018

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3 answers

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UGC NET CSE | July 2018 | Part 2 | Question: 94
What does the following logic diagram represent? Synchronous Counter Ripple Counter Combinational Circuit Mod 2 Counter

Pooja Khatri asked in Digital Logic Jul 13, 2018

by Pooja Khatri

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3 votes

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MultiSubject (CO, DIgital, DS)
A 4-bit modulo-16 ripple counter uses JK flip-flops. If the propagation delay of each FF is 100 ns, the maximum clock frequency that can be used is equal to: Ans 2.5MHz. I think it should be $\frac{1}{16*10^{-7}} = 0.625MHz$ ... minimum number of comparisons that will be needed in the worst case by the optimal algorithm for doing this is Ans = 840 I am getting 860.

Shubhanshu asked in Programming Jan 25, 2018

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2 votes

1 answer

10

made easy test series

rohit vishkarma asked in Digital Logic Jan 6, 2018

by rohit vishkarma

195 views

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Made_Easy_test
Pr0,Pr1,Pr2????

hs_yadav asked in Digital Logic Nov 30, 2017

593 views

2 votes

1 answer

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digital logic 3
in a 6 bit ripple counter, the MOD of UP couting is 14 , the MOD of down counting is........?

hem chandra joshi asked in Digital Logic Sep 23, 2017

by hem chandra joshi

404 views

5 votes

1 answer

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MadeEasy CBT 2017: Digital Logic - Digital Counter
Identify the mod value of the given riple counter 5 6 7 8

pC asked in Digital Logic Jan 23, 2017

by pC

1.8k views

1 vote

3 answers

14

Test by Bikram | Mock GATE | Test 1 | Question: 37
A pulse train with a frequency of $1$ $MHz$ is counted using a modulo $1024$ ripple counter built with $J-K$ flip flops. For proper operation of the counter, the maximum permissible propagation delay per flip flop stage is: $10 \: nsec$ $100 \: nsec$ $1000 \: nsec$ $100 \: microsec$

Bikram asked in GATE Jan 16, 2017

by Bikram

566 views

5 votes

1 answer

15

Digital
An eight stage ripple counter uses a flip-flop with propagation delay of 75 nanoseconds. The pulse width of the strobe is 50 ns. The frequency of the input signal which can be used for proper operation of the counter is approximately ______________

srestha asked in Digital Logic Nov 4, 2016

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16

UGC NET CSE | August 2016 | Part 3 | Question: 1
A ripple counter is a $(n)$ : Synchronous Counter Asynchronous counter Parallel counter None of the above

makhdoom ghaya asked in Digital Logic Sep 30, 2016

by makhdoom ghaya

650 views

1 vote

1 answer

17

UGC NET CSE | September 2013 | Part 3 | Question: 36
A binary ripple counter is required to count up to 16383. How many flip-flops are required? 16382 8191 512 14

go_editor asked in Digital Logic Jul 24, 2016

4.1k views

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Recent questions tagged ripple-counter-operation