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Recent questions tagged self-doubt
0
votes
0
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181
c language
in char data type ,plzzz tell me initilization can be seprated from declaration..
in char data type ,plzzz tell me initilization can be seprated from declaration..
saurabh111
252
views
saurabh111
asked
Nov 2, 2018
Programming in C
self-doubt
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2
votes
0
answers
182
SELF DOUBT
https://gateoverflow.in/39620/gate2016-2-41 HOW WE ARE DOING IN O(M+N) TIME ......WHAT IS PROCEDURE TO DO THAT ?
https://gateoverflow.in/39620/gate2016-2-41HOW WE ARE DOING IN O(M+N) TIME ......WHAT IS PROCEDURE TO DO THAT ?
eyeamgj
171
views
eyeamgj
asked
Oct 31, 2018
Algorithms
self-doubt
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0
votes
0
answers
183
SELF DOUBT
https://gateoverflow.in/449/gate2008-38 I AM NOT GETTING THAT WHY OPTION B IS NOT CORRECT FROM ANY EXPLANATION... PLZZ HELP..
https://gateoverflow.in/449/gate2008-38 I AM NOT GETTING THAT WHY OPTION B IS NOT CORRECT FROM ANY EXPLANATION...PLZZ HELP..
Deepanshu
119
views
Deepanshu
asked
Oct 30, 2018
CO and Architecture
co-and-architecture
self-doubt
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0
votes
0
answers
184
self doubt
RISC HAS MORE REGISTER THAN CISC . I KNOW THIS STATEMENT IS TRUE BUT I AM NOT GETTING ENOUGH RESOURCE FOR THIS POINT VALIDATION . AS CISC HAS MORE THAN RISC IN EVERYTHING LIKE ADDRESSING MODES , INSTRUCTIONS AND MANY OTHER THINGS so at times i also ... in cisc due to having not good explanation .so please someone help me with this question with any example or any other thing
RISC HAS MORE REGISTER THAN CISC . I KNOW THIS STATEMENT IS TRUE BUT I AM NOT GETTING ENOUGH RESOURCE FOR THIS POINT VALIDATION .AS CISC HAS MORE THAN RISC IN EVERYTHIN...
Deepanshu
240
views
Deepanshu
asked
Oct 30, 2018
CO and Architecture
co-and-architecture
risc
cisc
self-doubt
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3
votes
0
answers
185
Difference between efficency and throughput?
I am confused with this silly doubt.. someone please help me. To calculate efficiency of sliding window protocol we use formula Efficiency = 1/1+2a ------Formula1 i understood how this formula derived by series of steps. And the we ... I am not trying to mug up formulas but trying to understand how they are derived and how each term have its significance
I am confused with this silly doubt.. someone please help me.To calculate efficiency of sliding window protocol we use formulaEfficiency = 1/1+2a Formula1i understood...
vupadhayayx86
5.4k
views
vupadhayayx86
asked
Oct 26, 2018
Computer Networks
computer-networks
sliding-window
self-doubt
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0
votes
1
answer
186
SELF DOUBT TIME OMPLEXITY
https://gateoverflow.in/154097/find-the-value-of-p AND THE TIME COMPLEXITY WILL BE O(nlogn)??
https://gateoverflow.in/154097/find-the-value-of-p AND THE TIME COMPLEXITY WILL BE O(nlogn)??
eyeamgj
138
views
eyeamgj
asked
Oct 16, 2018
Algorithms
time-complexity
self-doubt
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0
votes
0
answers
187
self doubt
suppose we have 50 control signal and suppose 49 control signals are active, Q1:consider horizontal micro programed control unit what is the length of control word in bits? Q2: consider vertical micro programed control unit what is the length of control word in bits?
suppose we have 50 control signal and suppose 49 control signals are active,Q1:consider horizontal micro programed control unit what is the length of control word in bit...
eyeamgj
683
views
eyeamgj
asked
Oct 16, 2018
CO and Architecture
co-and-architecture
microprogramming
horizontal-microprogramming
numerical-answers
self-doubt
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0
votes
0
answers
188
self doubt
what is the principle of inclusion in cache . pleasse explain in simple terms
what is the principle of inclusion in cache . pleasse explain in simple terms
Deepanshu
283
views
Deepanshu
asked
Oct 15, 2018
CO and Architecture
co-and-architecture
cache-memory
inclusion
self-doubt
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0
votes
1
answer
189
SELF DOUBT REGISTER REFERENCE
MOV R1 #23 HOW MANY REGISTER REFERENCES ARE REQUIRED?
MOV R1 #23 HOW MANY REGISTER REFERENCES ARE REQUIRED?
eyeamgj
342
views
eyeamgj
asked
Oct 12, 2018
CO and Architecture
co-and-architecture
addressing-modes
self-doubt
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0
votes
3
answers
190
Number of 0 address instructions possible
How many maximum number of zero address instructions possible?
How many maximum number of zero address instructions possible?
Balaji Jegan
663
views
Balaji Jegan
asked
Oct 10, 2018
CO and Architecture
co-and-architecture
zero-address-instruction
self-doubt
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0
votes
0
answers
191
Self Doubt
What would be the worst case time complexity of an unreachable code? Let's say there are two parts to the code, where first part is if (0) with complexity O(n) and the else part with O(1). Something like this: if (0) { Time ... or we deduce it logically? Is there any resource to support this? How is time complexity calculated for unreachable code? Thanks Registered user 48
What would be the worst case time complexity of an unreachable code?Let's say there are two parts to the code, where first part is if (0) with complexity O(n) and the els...
Registered user 48
373
views
Registered user 48
asked
Oct 4, 2018
Algorithms
algorithms
self-doubt
programming
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0
votes
1
answer
192
self doubt
++*p and (*p)++ both are same????
++*p and (*p)++both are same????
eyeamgj
516
views
eyeamgj
asked
Oct 3, 2018
Programming in C
programming-in-c
pointers
self-doubt
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0
votes
0
answers
193
Self doubt CO
Say the processor runs at 600 MHz then what is CPU clock time?
Say the processor runs at 600 MHz then what is CPU clock time?
iarnav
433
views
iarnav
asked
Oct 3, 2018
CO and Architecture
co-and-architecture
cpu
clock-time
self-doubt
numerical-answers
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0
votes
0
answers
194
DIRECT CACHE
https://gateoverflow.in/863/gate2002-10 IN THE SOLUTION BY ARJUN SIR HOW THIS LINE IS JUSTIFYING THAT ALL WILL MAP TO DIFFERENT SET?????? So, since the ending address is not extending beyond these 9 bits,9 bits, all cache accesses are to diff sets.
https://gateoverflow.in/863/gate2002-10IN THE SOLUTION BY ARJUN SIR HOW THIS LINE IS JUSTIFYING THAT ALL WILL MAP TO DIFFERENT SET?????? So, since the ending address is n...
eyeamgj
227
views
eyeamgj
asked
Oct 1, 2018
CO and Architecture
co-and-architecture
cache-memory
self-doubt
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0
votes
0
answers
195
Gate questions
https://gateoverflow.in/1657/gate1998-1-20 https://gateoverflow.in/1300/gate2009-8-ugcnet-june2012-iii-58 The answer assumes execution means the execute phase in a pipelined system while in the other answer, execution means the execution of an entire instruction. How ... assume what? Option C is considered as wrong in the first link while it is the correct answer in the second link.
https://gateoverflow.in/1657/gate1998-1-20https://gateoverflow.in/1300/gate2009-8-ugcnet-june2012-iii-58The answer assumes execution means the execute phase in a pipeline...
gauravkc
377
views
gauravkc
asked
Sep 30, 2018
CO and Architecture
interrupts
co-and-architecture
self-doubt
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0
votes
0
answers
196
Self-doubt What events happen in Cache Access duration
What events happen when we say that a cache at level i is accessed? (I am able to use the cache formulas as given in textbooks and also most of the times, I arrive at the correct answer, but I want to fully understand the basic details ... duration? Do we include any extra time for STORING the data in the level (i-1)th cache as is done here ?
What events happen when we say that a cache at level i is accessed? (I am able to use the cache formulas as given in textbooks and also most of the times, I arrive at the...
Harsh Kumar
274
views
Harsh Kumar
asked
Sep 29, 2018
CO and Architecture
cache-memory
multilevel-cache
co-and-architecture
self-doubt
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0
votes
0
answers
197
Self-doubt Cache Access Time theory
What events happen when we say that a cache at level i is accessed. My understanding is the following events occur in the duration of an access time: The level i cache memory's RAM is accessed using the data bus. The cache RAM loads the required ... duration? Do we include any extra time for STORING the data in the level (i-1)th cache as is done here ?
What events happen when we say that a cache at level i is accessed.My understanding is the following events occur in the duration of an access time: The level i cache me...
Harsh Kumar
176
views
Harsh Kumar
asked
Sep 29, 2018
CO and Architecture
co-and-architecture
cache-memory
self-doubt
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1
votes
0
answers
198
self doubt
How stack addressing is related to Reentranecy ,can anyone explain it?
How stack addressing is related to Reentranecy ,can anyone explain it?
Prince Sindhiya
320
views
Prince Sindhiya
asked
Sep 27, 2018
CO and Architecture
co-and-architecture
addressing-modes
self-doubt
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0
votes
0
answers
199
self doubt
OPERAND FORWARDING work only when following cases 1) only when ALU(+,-,*,/) operation present 2) In only RAW Hazard . Am i right?
OPERAND FORWARDING work only when following cases 1) only when ALU(+,-,*,/) operation present2) In only RAW Hazard . Am i right?
VIDYADHAR SHELKE 1
231
views
VIDYADHAR SHELKE 1
asked
Sep 25, 2018
CO and Architecture
co-and-architecture
operand-forwarding
self-doubt
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0
votes
1
answer
200
Self Doubt
how we generally write addressing mode in instruction. eg. immediate addressing mode: add #5 1. Direct 2. Indirect 3. Register 4. Register Indirect 5. Indexed 6. Based 7. Displacement 8. Stack
how we generally write addressing mode in instruction. eg. immediate addressing mode: add #51. Direct2. Indirect3. Register4. Register Indirect5. Indexed6. Based7. Displa...
iamdeepakji
248
views
iamdeepakji
asked
Sep 19, 2018
CO and Architecture
co-and-architecture
addressing-modes
self-doubt
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–
0
votes
0
answers
201
#CO Gate 2009 Self Doubt.
Original question- https://gateoverflow.in/1314/gate2009-28 In the best answer selected, why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stage? In this question if we take the above approach, we will get different ... Refer this GATE 2004-IT question- https://gateoverflow.in/3690/gate2004-it-47 in this we are doing as the above approach.
Original question- https://gateoverflow.in/1314/gate2009-28In the best answer selected, why in 6th cycle we are introducing I4 {S1} while I3 {S2} hasn't gone to next stag...
iarnav
235
views
iarnav
asked
Sep 19, 2018
CO and Architecture
co-and-architecture
pipelining
self-doubt
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0
votes
1
answer
202
No of flip flops required
If there are total 21 different states in a system and there is one external input, then how many flip flops are required in case of : ripple counter ring counter johnson counter
If there are total 21 different states in a system and there is one external input, then how many flip flops are required in case of :ripple counterring counterjohnson co...
Balaji Jegan
574
views
Balaji Jegan
asked
Sep 16, 2018
Digital Logic
self-doubt
flip-flop
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0
votes
0
answers
203
Self doubt
Main mem block number is 4,6 and 8 . Then 8 is compalsory miss or conflict miss ????
Main mem block number is 4,6 and 8 . Then 8 is compalsory miss or conflict miss ????
abhishekmehta4u
233
views
abhishekmehta4u
asked
Sep 16, 2018
CO and Architecture
co-and-architecture
cache-memory
misses
self-doubt
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–
0
votes
0
answers
204
self doubt write back cache
https://gateoverflow.in/35154/write-back-and-write-through every thing is clear but a doubt is tht why only the case of dirty bit is considered ...and why the case of clean bit is left while solving ??? and when to take both cases??should be explicitly mentioned in the question??
https://gateoverflow.in/35154/write-back-and-write-through every thing is clear but a doubt is tht why only the case of dirty bit is considered ...and why the case of cle...
eyeamgj
173
views
eyeamgj
asked
Sep 15, 2018
CO and Architecture
co-and-architecture
cache-memory
write-back
self-doubt
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–
0
votes
0
answers
205
Doubt in memory hierarchy
What are the external connections in memory circuit ?
What are the external connections in memory circuit ?
Abbas Ahmad
205
views
Abbas Ahmad
asked
Sep 15, 2018
CO and Architecture
co-and-architecture
memory-hierarchy
self-doubt
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–
0
votes
0
answers
206
selfdoubt
https://gateoverflow.in/2078/gate2014-3-44 in this question the reason of dividing is that frequenies of operations are given in quantity not in percentage???
https://gateoverflow.in/2078/gate2014-3-44in this question the reason of dividing is that frequenies of operations are given in quantity not in percentage???
eyeamgj
137
views
eyeamgj
asked
Sep 13, 2018
CO and Architecture
co-and-architecture
cache-memory
self-doubt
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–
0
votes
1
answer
207
SELF DOUBT
https://gateoverflow.in/131079/coa-dma FOR BURST MODE IT SHOULD ALSO SYSTEM BUS??
https://gateoverflow.in/131079/coa-dmaFOR BURST MODE IT SHOULD ALSO SYSTEM BUS??
eyeamgj
322
views
eyeamgj
asked
Sep 13, 2018
CO and Architecture
co-and-architecture
dma
self-doubt
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–
0
votes
0
answers
208
Peter Linz Edition 4 Theorem 12.1 (Page No. 301)
How $H'$ ending with initial state $q_{0}$? Plz explain with the figure given
How $H'$ ending with initial state $q_{0}$? Plz explain with the figure given
srestha
196
views
srestha
asked
Sep 13, 2018
Theory of Computation
theory-of-computation
peter-linz
peter-linz-edition4
turing-machine
self-doubt
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–
0
votes
0
answers
209
Peter Linz Edition 4 Theorem 12.1 (Page No. 300)
Need some explanation on these two states. How from first state we can go to the last state as shown the symbol?
Need some explanation on these two states. How from first state we can go to the last state as shown the symbol?
srestha
253
views
srestha
asked
Sep 13, 2018
Theory of Computation
theory-of-computation
peter-linz
peter-linz-edition4
turing-machine
self-doubt
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–
0
votes
1
answer
210
self doubt
https://gateoverflow.in/130962/coa-memory answer for c is (2^16)*24 bits is correct??
https://gateoverflow.in/130962/coa-memoryanswer for c is (2^16)*24 bits is correct??
eyeamgj
353
views
eyeamgj
asked
Sep 12, 2018
CO and Architecture
co-and-architecture
self-doubt
+
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