Recent questions tagged sequential / GATE Overflow for GATE CSE

0 votes

1 answer

1

Counters
Is this statement true? Nonbinary counter means synchronous counter?

Is this statement true?Nonbinary counter means synchronous counter?

sunaina rawat

325 views

sunaina rawat asked Dec 3, 2017

1 votes

1 answer

2

Flip flops
Consider the complemented circuit shown below: If the initial value of the output Q1 Q0 is 00, then the next three values of Q1 Q0 are:- 10,01,01,00 10,01,11,00 10,01,00,01 10,01,10,00 Doubt:- I am getting a sequence which is not matching with any of the option

Consider the complemented circuit shown below:If the initial value of the output Q1 Q0 is 00, then the next three values of Q1 Q0 are:- 10,01,01,00 10,01,11,00 10,01,0...

akb1115

1.2k views

akb1115 asked Nov 8, 2017

0 votes

0 answers

3

Digital-Logic Flip-flop Counters
Qn) Ripple counter with preset works as? QN- 2) Construction of Decoder 4:16? QN- 3) 4 JK Flip-flops with high input. The frequency at output?

Qn) Ripple counter with preset works as?QN- 2) Construction of Decoder 4:16?QN- 3) 4 JK Flip-flops with high input. The frequency at output?

POOJAN SHAH

637 views

POOJAN SHAH asked Aug 24, 2017

1 votes

0 answers

4

From a practice problem set of Made Easy
This is a question in Made Easy sheet and is related to Master Slave JK Flip Flop. I understand the solution but while trying to get the answer using the timing diagram The answer I get is different from that in the option(00,01,11,10,00). Please verify my timing diagram shown in image and correct me where I am wrong

This is a question in Made Easy sheet and is related to Master Slave JK Flip Flop. I understand the solution but while trying to get the answer using the timing diagram T...

Aastha Mishra

622 views

Aastha Mishra asked Jul 31, 2017

2 votes

0 answers

5

Identify MOD of the Counter
Clock Q0 Q1 Q2 State 0 0 0 0 1 1 0 0 1 2 0 1 0 2 3 1 1 0 3 4 0 0 1 4 5 1 0 1 5 At clock t5 or lets say after 5 clock pulses Q0 and Q2 becomes 1 and through NAND gate they will become 0 and since preset ... connecting clock to the gate play any significance role? Doubt is similar to the one of the gate questions asked prviously : https://gateoverflow.in/1234/gate2007-36

ClockQ0Q1Q2State 00001100120102311034001451015At clock t5 or lets say after 5 clock pulses Q0 and Q2 becomes 1 and through NAND gate they will become 0 and since preset i...

yg92

4.6k views

yg92 asked Jan 22, 2017

2 votes

3 answers

6

Digital electronics
Given the sequence 010202010 is generated from a sequential circuit of n flip-flops. And these flip-flops generate the sequence respectively. What is the minimum value of n?

Given the sequence 010202010 is generated from a sequential circuit of n flip-flops. And these flip-flops generate the sequence respectively. What is the minimum value of...

Ravi_1511

1.2k views

Ravi_1511 asked Nov 18, 2016

0 votes

0 answers

7

Consider the following circuit of counter

Payal Rastogi

900 views

Payal Rastogi asked Jan 29, 2016

1 votes

1 answer

8

digital logic
How is the correct ans c?

How is the correct ans c?

UK

404 views

UK asked Jan 21, 2016

0 votes

2 answers

9

A switch tail ring counter is made by using a single D FF.
A switch-tail ring counter is made by using a single D FF. The resulting circuit is (a) SR flip-flop (b) JK flip-flop (c) D flip-flop (d) T flip-flop

A switch-tail ring counter is made by using a single D FF. The resulting circuit is (a) SR flip-flop (b) JK flip-flop (c) D flip-flop...

Payal Rastogi

16.3k views

Payal Rastogi asked Dec 25, 2015

0 votes

1 answer

10

Digital Logic Morris Mono 5.6
A sequential circuit with two $D$ flip-flops $A$ and $B$, two inputs $x$ and $y$, and one output $z$ is specified by the following next-state and output equations : $A(t+1)= x'y + xB$ $B(t+1)= x'A + xB$ $z = A$ (a) Draw the logic diagram of the circuit. (b) List the state table for the sequential circuit. (c) Draw the corresponding state diagram.

A sequential circuit with two $D$ flip-flops $A$ and $B$, two inputs $x$ and $y$, and one output $z$ is specified by the following next-state and output equations : ...

Akash Kanase

2.5k views

Akash Kanase asked Dec 15, 2015

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