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Recent questions tagged sequential-circuit
2
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61
GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 16
Consider the $JK$ Flip flop made using NAND gates given below What is the characteristic equation of $JK$ Flip flop ? ( $Q$ represents the present state and $Q_{n}$ represents the next state of the flip flop) $Q_{n}=\overline{J} Q+K Q$ ... $Q_{n}=J Q+\overline{K} Q$ $Q_{n}=\overline{J} Q+K \overline{Q}$
Consider the $JK$ Flip flop made using NAND gates given belowWhat is the characteristic equation of $JK$ Flip flop ? ( $Q$ represents the present state and $Q_{n}$ repres...
GO Classes
201
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GO Classes
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Jun 2, 2022
Digital Logic
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goclasses
digital-logic
sequential-circuit
flip-flop
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3
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1
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62
GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 20
Consider the following circuit : If $A n, B n$ denote the next state corresponding to current states $A, B$ ... of states in the state transition diagram of this circuit that have a transition back to the same state is $2 .$
Consider the following circuit :If $A n, B n$ denote the next state corresponding to current states $A, B$ respectively, thenFor this circuit, which of the following is/a...
GO Classes
459
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GO Classes
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Jun 2, 2022
Digital Logic
goclasses2024-dl-3-weekly-quiz
goclasses
digital-logic
sequential-circuit
flip-flop
multiple-selects
2-marks
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2
votes
1
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63
GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 21
Consider the sequential circuit shown in the figure, where both flip-flops $\text{FD A}$ and $\text{FD B}$ used are positive edge-triggered $D$ flip-flops. The state of this circuit is represented by $(AB).$ This circuit is a $2$-bit complex ... $2.$ Number of PI for $D_{A}$ is $2$ and Number of EPI for $D_{B}$ is $3.$
Consider the sequential circuit shown in the figure, where both flip-flops “$\text{FD A}$” and “$\text{FD B}$” used are positive edge-triggered $D$ flip-flops. Th...
GO Classes
270
views
GO Classes
asked
Jun 2, 2022
Digital Logic
goclasses2024-dl-3-weekly-quiz
goclasses
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
flip-flop
digital-counter
2-marks
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2
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1
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64
GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 22
Consider the sequential circuit shown in the figure, where both flip-flops $\text{FD A}$ and $\text{FD B}$ used are positive edge-triggered $D$ flip-flops. The state of this circuit is represented by $(AB).$ This circuit is a ... when $x=1$. It works as a down counter when $x=1$ and works as a johnson counter when $x=0$.
Consider the sequential circuit shown in the figure, where both flip-flops “$\text{FD A}$” and “$\text{FD B}$” used are positive edge-triggered $D$ flip-flops. Th...
GO Classes
218
views
GO Classes
asked
Jun 2, 2022
Digital Logic
goclasses2024-dl-3-weekly-quiz
goclasses
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
flip-flop
digital-counter
2-marks
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1
votes
1
answer
65
GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 23
Consider the following circuit. What are the values of $P, Q, R$ after two cycles if $P=0, Q=1$ and $R=0$ to begin with? $011$ $101$ $100$ $111$
Consider the following circuit.What are the values of $P, Q, R$ after two cycles if $P=0, Q=1$ and $R=0$ to begin with?$011$$101$$100$$111$
GO Classes
154
views
GO Classes
asked
Jun 2, 2022
Digital Logic
goclasses2024-dl-3-weekly-quiz
goclasses
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
flip-flop
digital-counter
2-marks
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2
votes
1
answer
66
GO Classes Test Series 2023 | Digital Logic | Test 3 | Question: 25
Consider the following circuit. $10011000010$ is supplied to the "data" terminal in $11$ clock cycles. After that the values of $q_2 q_1 q_0$ are $000$ $010$ $101$ $111$
Consider the following circuit.$10011000010$ is supplied to the "data" terminal in $11$ clock cycles. After that the values of $q_2 q_1 q_0$ are$000$$010$$101$$111$
GO Classes
255
views
GO Classes
asked
Jun 2, 2022
Digital Logic
goclasses2024-dl-3-weekly-quiz
goclasses
digital-logic
sequential-circuit
synchronous-asynchronous-circuits
flip-flop
digital-counter
2-marks
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11
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3
answers
67
GATE CSE 2021 Set 1 | Question: 28
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below: Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next three states? $011,101,000$ $001,010,111$ $011,101,111$ $001,010,000$
Consider a $3$-bit counter, designed using $T$ flip-flops, as shown below:Assuming the initial state of the counter given by $\text{PQR}$ as $000$, what are the next thre...
Arjun
7.4k
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Arjun
asked
Feb 18, 2021
Digital Logic
gatecse-2021-set1
digital-logic
sequential-circuit
digital-counter
2-marks
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1
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1
answer
68
NIELIT Scientific Assistant A 2020 November: 85
Which flip-flop is used to make all types of shift registers? JK flip-flop D flip-flop T flip-flop All the options
Which flip-flop is used to make all types of shift registers?JK flip-flopD flip-flopT flip-flopAll the options
gatecse
546
views
gatecse
asked
Dec 9, 2020
Digital Logic
nielit-sta-2020
digital-logic
sequential-circuit
flip-flop
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4
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69
NIELIT 2017 OCT Scientific Assistant A (IT) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple cou...
admin
968
views
admin
asked
Aug 28, 2020
Digital Logic
nielit2017oct-assistanta-it
digital-logic
sequential-circuit
flip-flop
digital-counter
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0
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3
answers
70
NIELIT 2017 OCT Scientific Assistant A (CS) - Section D: 9
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is $\text{S-R}$ Flip-flop with inputs $X = R$ and $Y=S$ $\text{S-R}$ ... $X = J$ and $Y=K$ $\text{J-K}$ Flip-flop with inputs $X = K$ and $Y=J$
A sequential circuit using D flip-flop and logic gates is shown in Figure, where $X$ and $Y$ are the inputs and $Z$ is the output. The circuit is$\text{S-R}$ Flip-flop wi...
admin
2.1k
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admin
asked
Aug 28, 2020
Digital Logic
nielit2017oct-assistanta-cs
digital-logic
sequential-circuit
flip-flop
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71
NIELIT 2017 OCT Scientific Assistant A (CS) - Section D: 10
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple counter and the synchronous counter be $R$ and $S$ respectively, then $R = 10$ ns, $S = 40$ ns $R = 40$ ns, $S = 10$ ns $R = 10$ ns, $S = 30$ ns $R = 30$ ns, $S = 10$ ns
A $4$ bit ripple counter and a $4$ bit synchronous counter are made using flip-flops having a propagation delay of $10$ ns each. If the worst case delay in the ripple cou...
admin
962
views
admin
asked
Aug 28, 2020
Digital Logic
nielit2017oct-assistanta-cs
digital-logic
sequential-circuit
flip-flop
digital-counter
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2
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72
NIELIT 2016 MAR Scientist C - Section C: 37
A sequential circuit outputs a $\text{ONE}$ when an even number$(>0)$ of one’s are input; otherwise the output is $\text{ZERO}.$ The minimum number of states required is $0$ $1$ $2$ $3$
A sequential circuit outputs a $\text{ONE}$ when an even number$(>0)$ of one’s are input; otherwise the output is $\text{ZERO}.$ The minimum number of states required i...
admin
1.2k
views
admin
asked
Apr 2, 2020
Digital Logic
nielit2016mar-scientistc
digital-logic
sequential-circuit
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73
NIELIT 2016 MAR Scientist C - Section C: 39
If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by $nT$ sec $(n-1)T$ sec $n/T$ sec $(2n-1)T$ sec
If a clock with time period $“T”$ is used with $n$ stage shift register, then output of final stage will be delayed by$nT$ sec$(n-1)T$ sec$n/T$ sec$(2n-1)T$ sec
admin
1.3k
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admin
asked
Apr 2, 2020
Digital Logic
nielit2016mar-scientistc
digital-logic
sequential-circuit
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74
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 19
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip-flops Clock input of one flip-flop
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied toClock input of all flip-flops$J$ and $K$ input of one flip-flop$J$ and $K$ input of...
admin
506
views
admin
asked
Apr 1, 2020
Digital Logic
nielit2017oct-assistanta-it
digital-logic
sequential-circuit
flip-flop
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1
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75
NIELIT 2017 OCT Scientific Assistant A (IT) - Section B: 33
The number of columns in a state table for a sequential circuit with $’m’$ flip flops and $’n’$ input is $m+n$ $m+2n$ $2m+n$ $2m+2n$
The number of columns in a state table for a sequential circuit with $’m’$ flip flops and $’n’$ input is$m+n$$m+2n$$2m+n$$2m+2n$
admin
1.6k
views
admin
asked
Apr 1, 2020
Digital Logic
nielit2017oct-assistanta-it
digital-logic
sequential-circuit
flip-flop
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1
votes
2
answers
76
NIELIT 2017 OCT Scientific Assistant A (CS) - Section C: 8
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied to Clock input of all flip-flops $J$ and $K$ input of one flip-flop $J$ and $K$ input of all flip flops Clock input of one flip-flop
In a ripple counter using edge-triggered $JK$ flip-flops, the pulse input is applied toClock input of all flip-flops$J$ and $K$ input of one flip-flop$J$ and $K$ input of...
admin
705
views
admin
asked
Apr 1, 2020
Digital Logic
nielit2017oct-assistanta-cs
digital-logic
sequential-circuit
flip-flop
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3
votes
2
answers
77
NIELIT 2016 MAR Scientist B - Section C: 3
The output of a sequential circuit depends on present inputs only past inputs only both present and past inputs present outputs only
The output of a sequential circuit depends on present inputs onlypast inputs onlyboth present and past inputspresent outputs only
admin
1.1k
views
admin
asked
Mar 31, 2020
Digital Logic
nielit2016mar-scientistb
digital-logic
sequential-circuit
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3
votes
1
answer
78
NIELIT 2016 MAR Scientist B - Section C: 4
In a ripple counter using edge triggered $JK$ flip-flops, the pulse input is applied to the clock input of all flip-flops clock input of one flip-flop $J$ and $K$ inputs of all flip-flops $J$ and $K$ inputs of one flip flop
In a ripple counter using edge triggered $JK$ flip-flops, the pulse input is applied to theclock input of all flip-flopsclock input of one flip-flop$J$ and $K$ inputs of ...
admin
2.5k
views
admin
asked
Mar 31, 2020
Digital Logic
nielit2016mar-scientistb
digital-logic
sequential-circuit
flip-flop
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3
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2
answers
79
NIELIT 2016 DEC Scientist B (IT) - Section B: 35
What will be the final output of D flip-Flop if the input string is $0010011100$? $1$ $0$ Don’t Care None of the above
What will be the final output of D flip-Flop if the input string is $0010011100$?$1$$0$Don’t CareNone of the above
admin
2.3k
views
admin
asked
Mar 31, 2020
Digital Logic
nielit2016dec-scientistb-it
digital-logic
sequential-circuit
flip-flop
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2
votes
1
answer
80
NIELIT 2016 DEC Scientist B (CS) - Section B: 35
What will be the final output of D Flip-Flop, if the input string is $11010011$? $1$ $0$ Don’t Care None of the above
What will be the final output of D Flip-Flop, if the input string is $11010011$?$1$$0$Don’t CareNone of the above
admin
868
views
admin
asked
Mar 31, 2020
Digital Logic
nielit2016dec-scientistb-cs
digital-logic
sequential-circuit
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4
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1
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81
ISRO2020-80
A new flipflop with inputs $X$ and $Y$ ... $(X\wedge \overline{Q })\vee (Y \wedge Q)$ $(X\wedge \overline{Q })\vee (\overline{Y } \wedge Q)$
A new flipflop with inputs $X$ and $Y$, has the following property$$\begin{array}{|c|c|c|}\hline \bf{X}& \bf{Y}& \bf{Current\ state}&\bf{ Next\ state} \\\hline 0&0&Q&...
Satbir
2.8k
views
Satbir
asked
Jan 13, 2020
Digital Logic
isro-2020
digital-logic
sequential-circuit
flip-flop
normal
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