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Recent questions tagged shift-registers
2
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GO Classes Test Series 2024 | Mock GATE | Test 14 | Question: 59
Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register using the parallel load mechanism (i.e., shift=0 ... consecutive positive edges of the clock signal we need to keep shift=1 such that zero detect is activated to a 1?
Consider the shift register circuit shown in below figure. Assume that $\mathbf{I}_3 \mathbf{I}_2 \mathbf{I}_1 \mathbf{I}_0=0101$ has been loaded in the 4-bit register us...
GO Classes
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GO Classes
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Feb 5
Digital Logic
goclasses2024-mockgate-14
numerical-answers
digital-logic
sequential-circuit
shift-registers
2-marks
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0
votes
1
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2
ISRO 2024
The time delay obtained through an 8-bit serial register with 400 MHz clock is: 20 ns 2.5 µs 20 µs 2.5 µs
The time delay obtained through an 8-bit serial register with 400 MHz clock is:20 ns2.5 µs20 µs2.5 µs
Ramayya
241
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Ramayya
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Jan 7
Digital Logic
isro-2024
shift-registers
digital-circuits
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1
votes
0
answers
3
MadeEasy Full Length Test 2019: Digital Logic - Shift Registers
Please answer??
Please answer??
raahul
633
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raahul
asked
Jan 17, 2019
Digital Logic
digital-logic
shift-registers
made-easy-test-series
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0
votes
1
answer
4
Digital Logic madeeasy
A 4 bit right shift register is shifting the data to the right for every clock pulse. The serial input D is derived by using XOR gates as shown. After 3 clock pulses the content in the register is to be 1010 at Q0Q1Q2Q3. What were the initial contents of the register? 1100 1010 0011 0101 I’m getting the answer as 0101 but it’s given 0011
A 4 bit right shift register is shifting the data to the right for every clock pulse. The serial input D is derived by using XOR gates as shown. After 3 clock pulses the ...
Sambhrant Maurya
2.0k
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Sambhrant Maurya
asked
Jan 4, 2019
Digital Logic
digital-logic
sequential-circuit
shift-registers
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0
votes
1
answer
5
MadeEasy Workbook: Digital Logic - Shift Registers
How to solve this question?
How to solve this question?
Jyoti Kumari97
794
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Jyoti Kumari97
asked
Dec 31, 2018
Digital Logic
digital-logic
shift-registers
made-easy-booklet
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0
votes
2
answers
6
MadeEasy Workbook: Digital Logic - Shift Registers
a 4 bit serial in parallel out shift register is used with a feedback as shown in figure below the shifting sequences q3 - >q2-> q1- > q0. if the output is initially 0000, the no of clock pulses after which t the output will repeat itself is
a 4 bit serial in parallel out shift register is used with a feedback as shown in figure below the shifting sequences q3 - >q2- q1- q0. if the output is initially 0000, ...
Jyoti Kumari97
1.9k
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Jyoti Kumari97
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Dec 31, 2018
Digital Logic
digital-logic
shift-registers
made-easy-booklet
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0
votes
1
answer
7
Ugc/gate cse paper
In right shift register, right shift operation of binary $11$ gives $5.5$ $5$ $6$ $\text{none of these}$
In right shift register, right shift operation of binary $11$ gives$5.5$$5$$6$$\text{none of these}$
Gjk
1.0k
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Gjk
asked
May 20, 2018
Digital Logic
co-and-architecture
shift-registers
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0
votes
1
answer
8
Testbook Test Series: Digital Logic - Shift Registers
Verify Please !
Verify Please !
saxena0612
289
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saxena0612
asked
Dec 13, 2017
Digital Logic
testbook-test-series
digital-logic
shift-registers
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1
votes
1
answer
9
Shift Registor
How many clock pulses are required for giving input and taking the output of n bit Serial-in-serial-out-shift-register?
How many clock pulses are required for giving input and taking the output of n bit Serial-in-serial-out-shift-register?
Nikhil Patil
1.7k
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Nikhil Patil
asked
Oct 16, 2017
Digital Logic
digital-logic
shift-registers
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1
votes
2
answers
10
ISRO2016-ECE Digital logic
Which shift register counter requires the most decoding circuitry? Johnson Counter Ring Counter Ripple Counter $\text{MOD}$ counter
Which shift register counter requires the most decoding circuitry?Johnson CounterRing CounterRipple Counter$\text{MOD}$ counter
sh!va
2.9k
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sh!va
asked
Feb 21, 2017
Digital Logic
isro2016-ece
digital-logic
sequential-circuit
digital-counter
shift-registers
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2
votes
1
answer
11
MadeEasy Subject Test: Digital Logic - Shift Registers
Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock?
Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied withA 4 bit data 1011 is applied to the shift register 1. What is ...
Pankaj Joshi
8.1k
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Pankaj Joshi
asked
Jan 26, 2017
Digital Logic
made-easy-test-series
digital-logic
shift-registers
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2
votes
1
answer
12
Digital
ans should be 10??
ans should be 10??
Supremo
422
views
Supremo
asked
Jan 19, 2017
Digital Logic
digital-logic
shift-registers
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6
votes
0
answers
13
GATE CSE 1989 | Question: 5b
It is required to implement a stack using bidirectional shift registers providing stack underflow and overflow detection capability. How many shift registers are needed for a stack capacity of $nk$-bit words? Show the schematic diagram of the implementation, clearly indicating all the data and control lines.
It is required to implement a stack using bidirectional shift registers providing stack underflow and overflow detection capability.How many shift registers are needed fo...
makhdoom ghaya
593
views
makhdoom ghaya
asked
Nov 30, 2016
Digital Logic
descriptive
gate1989
digital-logic
sequential-circuit
shift-registers
unsolved
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–
18
votes
3
answers
14
GATE CSE 1987 | Question: 13-a
The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ ... $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$
The below figure shows four $\text{D}$-type flip-flops connected as a shift register using a $\text{XOR}$ gate. The initial state and three subsequent states for three cl...
makhdoom ghaya
3.7k
views
makhdoom ghaya
asked
Nov 15, 2016
Digital Logic
gate1987
digital-logic
circuit-output
sequential-circuit
digital-counter
shift-registers
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0
votes
1
answer
15
MadeEasy Test Series: Digital Logic -Shift Registers
Q.42 Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock? 11 12 13 14 Please answer !
Q.42Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied withA 4 bit data 1011 is applied to the shift register 1. What...
Akash Kanase
1.7k
views
Akash Kanase
asked
Dec 19, 2015
Digital Logic
digital-logic
shift-registers
made-easy-test-series
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5
votes
0
answers
16
GATE CSE 1991 | Question: 6,b
Design a $1024$ bit serial-in/serial-out unidirectional shift register using a $1K\times 1 $bit RAM with a data input $D_{in}$, data output $D_{out}$ and control input $\text{READ}/\overline{\text{WRITE}}$. You may assume the availability of standard SSI and MSI components such as gates, registers and counters.
Design a $1024$ bit serial-in/serial-out unidirectional shift register using a $1K\times 1 $bit RAM with a data input $D_{in}$, data output $D_{out}$ and control input $...
ibia
765
views
ibia
asked
Nov 14, 2015
Digital Logic
gate1991
digital-logic
sequential-circuit
shift-registers
out-of-gate-syllabus
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6
votes
2
answers
17
GATE CSE 1991 | Question: 06,a
Using $\text{D}$ flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines: Clock $\text{CLK}$ Three parallel data inputs $A, B, C$ Serial input $S$ Control input $\text{LOAD} / \overline{\text{SHIFT}}$.
Using $\text{D}$ flip-flop gates, design a parallel-in/serial-out shift register that shifts data from left to right with the following input lines:Clock $\text{CLK}$Thre...
Kathleen
1.5k
views
Kathleen
asked
Sep 12, 2014
Digital Logic
gate1991
digital-logic
difficult
sequential-circuit
flip-flop
shift-registers
descriptive
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