Recent questions tagged shift-registers

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1

MadeEasy Full Length Test 2019: Digital Logic - Shift Registers
Please answer??

asked Jan 17, 2019 in Digital Logic by raahul Active (1.4k points) | 111 views

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2

Digital Logic madeeasy
A 4 bit right shift register is shifting the data to the right for every clock pulse. The serial input D is derived by using XOR gates as shown. After 3 clock pulses the content in the register is to be 1010 at Q0Q1Q2Q3. What were the initial contents of the register? 1100 1010 0011 0101 I’m getting the answer as 0101 but it’s given 0011

asked Jan 4, 2019 in Digital Logic by Sambhrant Maurya Active (3.9k points) | 66 views

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3

MadeEasy Workbook: Digital Logic - Shift Registers
How to solve this question?

asked Dec 31, 2018 in Digital Logic by Jyoti Kumari97 (187 points) | 96 views

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4

MadeEasy Workbook: Digital Logic - Shift Registers
a 4 bit serial in parallel out shift register is used with a feedback as shown in figure below the shifting sequences q3 - >q2-> q1- > q0. if the output is initially 0000, the no of clock pulses after which t the output will repeat itself is

asked Dec 31, 2018 in Digital Logic by Jyoti Kumari97 (187 points) | 121 views

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5

Ugc/gate cse paper
In right shift register, right shift operation of binary $11$ gives $5.5$ $5$ $6$ $\text{none of these}$

asked May 20, 2018 in Digital Logic by Gjk (5 points) | 66 views

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6

Testbook Test Series: Digital Logic - Shift Registers
Verify Please !

asked Dec 13, 2017 in Digital Logic by saxena0612 Boss (11.9k points) | 61 views

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1 answer

7

Shift Registor
How many clock pulses are required for giving input and taking the output of n bit Serial-in-serial-out-shift-register?

asked Oct 16, 2017 in Digital Logic by Nikhil Patil Junior (505 points) | 248 views

+2 votes

1 answer

8

MadeEasy Subject Test: Digital Logic - Shift Registers
Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock?

asked Jan 26, 2017 in Digital Logic by Pankaj Joshi Active (2.7k points) | 1.3k views

+2 votes

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9

Digital
ans should be 10??

asked Jan 19, 2017 in Digital Logic by Supremo (389 points) | 75 views

+5 votes

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10

GATE1989-5b
It is required to implement a stack using bidirectional shift registers providing stack under flow and overflow detection capability. How many shift registers are needed for a stack capacity of $n$ $k-$bit words? Show the schematic diagram of the implementation, clearly indicating all the data and control lines.

asked Dec 1, 2016 in Digital Logic by makhdoom ghaya Boss (30.8k points) | 208 views

+12 votes

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11

GATE1987-13-a
The below figure shows four D-type flip-flops connected as a shift register using a $XOR$ gate. The initial state and three subsequent states for three clock pulses are also given. State $Q_{A}$ $Q_{B}$ $Q_{C}$ $Q_{D}$ Initial $1$ $1$ $1$ $1$ After the first clock $0$ $1$ ... $0$ $0$ $1$ The state $Q_{A} Q_{B} Q_{C} Q_{D}$ after the fourth clock pulse is $0000$ $1111$ $1001$ $1000$

asked Nov 15, 2016 in Digital Logic by makhdoom ghaya Boss (30.8k points) | 922 views

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12

MadeEasy Test Series: Digital Logic -Shift Registers
Q.42 Three 4 bit shift registers are connected in cascade as shown in figure below. Each register is applied with A 4 bit data 1011 is applied to the shift register 1. What is the minimum number of clock pulses required to get same input data at output are with same clock? 11 12 13 14 Please answer !

asked Dec 19, 2015 in Digital Logic by Akash Kanase Boss (41.9k points) | 344 views

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