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Recent questions tagged speedup

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Question on Pipelining
In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If 70% of the conditional branches are taken, calculate % loss of speed-up due to branch instructions. It is very difficult to understand this question and solve it. Please help.

Swarnava Bose asked in CO and Architecture Jul 3

by Swarnava Bose

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Program runs in 100s . Multiplies 80 % of program . Designer M can improve speedup of multiply operations . Now , I am a user and I need to make MY program 5 times faster . How much speedup of multiply instructions should M achieve to allow me to reach my overall speedup goal ?

Sara86568 asked in CO and Architecture Jun 21

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speedup in pipelining made easy & nptel
Which approach is correct? ASSIGNMENT LINK :-- https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdf nptel assignment q-1 Caption

farmanahmed888 asked in CO and Architecture Jan 6

by farmanahmed888

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ISRO | ISRO CS 2020 | Question 6
Consider a 5-segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (If an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline.). (A) 5 (B) 4.03 (C) 4.81 (D) 4.17

ProtonicRED asked in CO and Architecture Dec 14, 2021

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3 votes

3 answers

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NIELIT 2016 DEC Scientist B (CS) - Section B: 23
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$

Lakshman Patel RJIT asked in CO and Architecture Mar 31, 2020

by Lakshman Patel RJIT

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2 votes

1 answer

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UGC NET CSE | June 2019 | Part 2 | Question: 20
Suppose that a computer program takes $100$ seconds of execution time on a computer with multiplication operation responsible for $80$ seconds of this time. How much do you have to improve the speed of the multiplication operation if you are ... this program four times faster? $14$ times faster $15$ times faster $16$ times faster $17$ times faster

Arjun asked in CO and Architecture Jul 2, 2019

by Arjun

3.4k views

1 vote

1 answer

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MadeEasy Full Length Test 2019: CO & Architecture - Speedup

jatin khachane 1 asked in CO and Architecture Jan 23, 2019

by jatin khachane 1

289 views

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Made Easy
A hypothetical 5 stage processor is designed in which branch is predicted at 3 stage and each stage takes 1 cycle to compute its task. If f is the probability of an instruction being a branch instruction then what is the value of F such that speed up is atleast 3?

anjali007 asked in CO and Architecture Jan 23, 2019

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Pipeline Efficiency
A pipeline has a speedup factor of 5 and operating at 70% efficiency. How many stages are there in the pipeline?

jatin khachane 1 asked in CO and Architecture Jan 22, 2019

by jatin khachane 1

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bts1jimin asked in CO and Architecture Jan 21, 2019

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ME mock 1
In an enhanced CPU, the speed of a floating point operations has been increased by 30% and the speed of a fixed point operations has been increased by 20%. In the original design floating point operations used to take twice the time compared to fixed point ... number of floating point instructions to the number of fixed point instructions is 2 : 3 is ________. (Upto 2 decimal places)

balchandar reddy san asked in CO and Architecture Jan 19, 2019

by balchandar reddy san

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1 vote

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Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.

Nandkishor3939 asked in CO and Architecture Jan 19, 2019

by Nandkishor3939

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MadeEasy Test Series: CO & Architecture - Speedup
A hypothetical processor on cache read miss require one clock to send an address to MM and eight clock cycle to access a 64 bit word from MM to processor cache.miss rate of read is decreased from 14.8% to 2.6% when line size of cache is ... bz , the complete line got transfer when request of one word is made in ans key it is 4*(1+8) mentioned

Learner_jai asked in CO and Architecture Jan 17, 2019

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ME TEST SERIES QUESTION ON PIPELINE

Shankar Kakde asked in CO and Architecture Jan 17, 2019

by Shankar Kakde

210 views

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made easy
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability of an instruction being branch instruction then the value of f such that speedup is atleast 3 is____

Harshit Bajpai asked in CO and Architecture Jan 14, 2019

by Harshit Bajpai

538 views

1 vote

3 answers

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MadeEasy Subject Test: CO & Architecture - Cache Memory
A cache memory is 30 times faster than main memory (MM) and 50% of the time cache is referred for the execution of instruction. The performance is gained by introducing this cache is ________. What I did EMAT = 0.5(M/30)+0.5(M/30+M) = 32M/60 speed up= (M)/32M/60) =60/32=1.875 answer given is 1.90-1.97 (using amdhal’s law)

Shivam Kasat asked in CO and Architecture Jan 13, 2019

by Shivam Kasat

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madeeasy
Consider a 5 stage pipeline with IF , ID, EX, WB and MA having latencies (in ms) 3,8,5,6,4. What is average CPI of non pipeline CPU when speed up achieved by to pipeline is 4? I think answer is wrong For non pipe line total time = Total number of ... * time for each cycle calculation For pipeline version total time = Total number of instruction * max(3,8,5,6,4) So No role of CPI

mehul vaidya asked in CO and Architecture Jan 13, 2019

by mehul vaidya

175 views

2 votes

1 answer

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MadeEasy Test Series: CO & Architecture - Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to ... up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)

Jay Bhutada 1 asked in CO and Architecture Jan 9, 2019

by Jay Bhutada 1

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garimanand asked in CO and Architecture Jan 6, 2019

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2 answers

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Speed up factor
Pipeline system has 4 stages and each stage takes 10ns. 30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up factor compare to same non pipelines, If there are 1000 instructions.

Alina asked in CO and Architecture Jan 1, 2019

by Alina

1.6k views

1 vote

1 answer

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ME test series
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided into 2 sub stages ... of the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825

newdreamz a1-z0 asked in CO and Architecture Dec 25, 2018

by newdreamz a1-z0

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made easy 2019
consider a system 1 with frequency 4GHz, Utkarsh runs a program designed to sort the integer in increasing order takes 10s to execute on this system. Utkarsh is designing a new system (system 2) to run the same program in 6sec.if increasing the clock rate will require 1.2 as many cycles for system 2,the clock rate of system 2 is ______________GHz.

Gate Fever asked in CO and Architecture Dec 22, 2018

298 views

1 vote

1 answer

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Calculate speed up ratio of pipeline
Non pipelined system takes 130ns to process an instruction . A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.

Alina asked in CO and Architecture Dec 21, 2018

by Alina

14.0k views

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Find speed up ratio
Non pipelined system takes 130 ns to process an instruction. A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.

Alina asked in CO and Architecture Dec 21, 2018

by Alina

623 views

2 votes

3 answers

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gatebook COA test
Consider a program being run on a processor. A modification in processor design caused 30% of the program to speed up by ten times while three fourth of the remaining program has a speed up of 80 and 40% of the remaining part of the program performs poorer ... by 50%. The remaining program has a speedup of 1. The overall speedup of the program exact to two decimal places is:-

sushmita asked in CO and Architecture Dec 18, 2018

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Recent questions tagged speedup