Recent questions tagged speedup / GATE Overflow for GATE CSE

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UGC NET CSE | June 2008 | Part 2 | Question: 46
Amdahl's law states that the maximum speedup $\text{S}$ achievable by a parallel computer with ' $\mathrm{p}$ ' processors is given by : $\mathrm{S} \leq \mathrm{f}+(1-\mathrm{f}) / \mathrm{p}$ ... $\mathrm{S} \leq 1 /[1-\mathrm{f}+\mathrm{f} / \mathrm{p}]$

Amdahl's law states that the maximum speedup $\text{S}$ achievable by a parallel computer with ' $\mathrm{p}$ ' processors is given by :$\mathrm{S} \leq \mathrm{f}+(1-\ma...

admin

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admin asked Jan 6

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1 answer

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Unacadmey book
If we have a non pipeline processor which has a cycle time of 40 ns and average CPI of 5.4 .Assuming a 5 stage pipeline model calculate the speed up of pipeline over non pipeline processor.

If we have a non pipeline processor which has a cycle time of 40 ns and average CPI of 5.4 .Assuming a 5 stage pipeline model calculate the speed up of pipeline over non ...

Praful jha

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Praful jha asked Jul 8, 2023

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1 answer

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Question on Pipelining
In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If 70% of the conditional branches are taken, calculate % loss of speed-up due to branch instructions. It is very difficult to understand this question and solve it. Please help.

In a pipeline the maximum ideal speed-up is 5. Let the percentage of unconditional branches in a set of typical program be 5% and that of conditional branches be 10%. If ...

Swarnava Bose

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Swarnava Bose asked Jul 2, 2022

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1 answer

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Program runs in 100s . Multiplies 80 % of program . Designer M can improve speedup of multiply operations . Now , I am a user and I need to make MY program 5 times faster . How much speedup of multiply instructions should M achieve to allow me to reach my overall speedup goal ?

The program runs in 100s. Multiplies 80 % of the program. Designer M can improve the speedup of multiply operations. Now, I am a user and I need to make MY program 5 time...

Sara86568

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Sara86568 asked Jun 21, 2022

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2 answers

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speedup in pipelining made easy & nptel
Which approach is correct? ASSIGNMENT LINK :-- https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdf nptel assignment q-1 Caption

Which approach is correct?ASSIGNMENT LINK : https://nptel.ac.in/content/storage2/courses/106105163/ASSIGNMENT-SOLUTION-WEEK11.pdfnptel assignment q-1 Caption

farmanahmed888

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farmanahmed888 asked Jan 6, 2022

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1 answer

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ISRO | ISRO CS 2020 | Question 6
Consider a 5-segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to execute 100 instructions. (If an average, every five cycles, a bubble due to data hazard has to be introduced in the pipeline.). (A) 5 (B) 4.03 (C) 4.81 (D) 4.17

Consider a 5-segment pipeline with a clock cycle time 20 ns in each sub operation. Find out the approximate speed-up ratio between pipelined and non-pipelined system to e...

ProtonicRED

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ProtonicRED asked Dec 14, 2021

3 votes

1 answer

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GATE Overflow Test Series | Mock GATE | Test 3 | Question: 54
Consider a five-stage pipeline with ideal CPI. Assume that $25\%$ of the instructions executed are branch instructions out of which $70\%$ are taken branches. The pipeline architecture is such that there is no penalty for a non-taken branch whereas ... $1$ cycle. What will be the effective pipeline speedup? $4.44$ $4.59$ $4.25$ $4.66$

Consider a five-stage pipeline with ideal CPI. Assume that $25\%$ of the instructions executed are branch instructions out of which $70\%$ are taken branches. The pipelin...

gatecse

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gatecse asked Jan 26, 2021

13 votes

2 answers

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GATE Overflow Test Series | Mock GATE | Test 2 | Question: 55
Consider a five-stage pipeline with ideal CPI. Assume that $25\%$ of the instructions executed are branch instructions out of which $75\%$ are taken branches. If the branch target is known at the end of EX stage, what will be the ... prediction and branch misprediction penalty on average is $10$ cycles? $3.34$ $3.07$ $4.00$ $4.11$

Consider a five-stage pipeline with ideal CPI. Assume that $25\%$ of the instructions executed are branch instructions out of which $75\%$ are taken branches. If the bran...

gatecse

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gatecse asked Jan 17, 2021

4 votes

3 answers

9

NIELIT 2016 DEC Scientist B (CS) - Section B: 23
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$

A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration...

admin

2.3k views

admin asked Mar 31, 2020

2 votes

1 answer

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UGC NET CSE | June 2019 | Part 2 | Question: 20
Suppose that a computer program takes $100$ seconds of execution time on a computer with multiplication operation responsible for $80$ seconds of this time. How much do you have to improve the speed of the multiplication operation if you are ... this program four times faster? $14$ times faster $15$ times faster $16$ times faster $17$ times faster

Suppose that a computer program takes $100$ seconds of execution time on a computer with multiplication operation responsible for $80$ seconds of this time. How much do y...

Arjun

6.0k views

Arjun asked Jul 2, 2019

1 votes

1 answer

11

MadeEasy Full Length Test 2019: CO & Architecture - Speedup

jatin khachane 1

467 views

jatin khachane 1 asked Jan 23, 2019

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1 answer

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Made Easy
A hypothetical 5 stage processor is designed in which branch is predicted at 3 stage and each stage takes 1 cycle to compute its task. If f is the probability of an instruction being a branch instruction then what is the value of F such that speed up is atleast 3?

A hypothetical 5 stage processor is designed in which branch is predicted at 3 stage and each stage takes 1 cycle to compute its task. If f is the probability of an instr...

anjali007

442 views

anjali007 asked Jan 23, 2019

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2 answers

13

Pipeline Efficiency
A pipeline has a speedup factor of 5 and operating at 70% efficiency. How many stages are there in the pipeline?

A pipeline has a speedup factor of 5 and operating at 70% efficiency. How many stages are there in the pipeline?

jatin khachane 1

2.2k views

jatin khachane 1 asked Jan 22, 2019

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0 answers

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Speedup

bts1jimin

302 views

bts1jimin asked Jan 21, 2019

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ME mock 1
In an enhanced CPU, the speed of a floating point operations has been increased by 30% and the speed of a fixed point operations has been increased by 20%. In the original design floating point operations used to take twice the time compared to fixed point ... number of floating point instructions to the number of fixed point instructions is 2 : 3 is ________. (Upto 2 decimal places)

In an enhanced CPU, the speed of a floating point operations has been increased by 30% and the speed of a fixed point operations has been increased by 20%. In the origina...

balchandar reddy san

289 views

balchandar reddy san asked Jan 19, 2019

1 votes

0 answers

16

Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.

In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages ope...

Nandkishor3939

776 views

Nandkishor3939 asked Jan 19, 2019

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0 answers

17

MadeEasy Test Series: CO & Architecture - Speedup
A hypothetical processor on cache read miss require one clock to send an address to MM and eight clock cycle to access a 64 bit word from MM to processor cache.miss rate of read is decreased from 14.8% to 2.6% when line size of cache is ... bz , the complete line got transfer when request of one word is made in ans key it is 4*(1+8) mentioned

A hypothetical processor on cache read miss require one clock to send an address to MM and eight clock cycle to access a 64 bit word from MM to processor cache.miss rate ...

Learner_jai

367 views

Learner_jai asked Jan 17, 2019

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1 answer

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ME TEST SERIES QUESTION ON PIPELINE

Shankar Kakde

449 views

Shankar Kakde asked Jan 16, 2019

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2 answers

19

made easy
A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability of an instruction being branch instruction then the value of f such that speedup is atleast 3 is____

A hypothetical 5 stage pipeline processor is designed in which branch is predicted at 3rd stage and each stage takes 1 cycle to compute its tasks. If f is the probability...

Harshit Bajpai

1.1k views

Harshit Bajpai asked Jan 14, 2019

1 votes

3 answers

20

MadeEasy Subject Test: CO & Architecture - Cache Memory
A cache memory is 30 times faster than main memory (MM) and 50% of the time cache is referred for the execution of instruction. The performance is gained by introducing this cache is ________. What I did EMAT = 0.5(M/30)+0.5(M/30+M) = 32M/60 speed up= (M)/32M/60) =60/32=1.875 answer given is 1.90-1.97 (using amdhal’s law)

A cache memory is 30 times faster than main memory (MM) and 50% of the time cache is referred for the execution of instruction. The performance is gained by introducing t...

Shivam Kasat

868 views

Shivam Kasat asked Jan 13, 2019

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21

madeeasy
Consider a 5 stage pipeline with IF , ID, EX, WB and MA having latencies (in ms) 3,8,5,6,4. What is average CPI of non pipeline CPU when speed up achieved by to pipeline is 4? I think answer is wrong For non pipe line total time = Total number of ... * time for each cycle calculation For pipeline version total time = Total number of instruction * max(3,8,5,6,4) So No role of CPI

Consider a 5 stage pipeline with IF , ID, EX, WB and MA having latencies (in ms) 3,8,5,6,4. What is average CPI of non pipeline CPU when speed up achieved by to pipeline ...

mehul vaidya

321 views

mehul vaidya asked Jan 12, 2019

2 votes

1 answer

22

MadeEasy Test Series: CO & Architecture - Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to ... up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)

A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor ...

Jay Bhutada 1

680 views

Jay Bhutada 1 asked Jan 9, 2019

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0 answers

23

made_easy

garimanand

163 views

garimanand asked Jan 6, 2019

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