The Gateway to Computer Science Excellence
For all GATE CSE Questions
Toggle navigation
Facebook Login
or
Email or Username
Password
Remember
Login
Register
|
I forgot my password
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
Prev
Blogs
New Blog
Exams
Recent questions tagged speedup
0
votes
1
answer
1
MadeEasy Full Length Test 2019: CO & Architecture - Speedup
asked
Jan 23
in
CO and Architecture
by
jatin khachane 1
Loyal
(
7.2k
points)
|
84
views
co-and-architecture
speedup
madeeasy-testseries-2019
made-easy-test-series
0
votes
0
answers
2
Speedup
asked
Jan 21
in
CO and Architecture
by
bts1jimin
(
199
points)
|
23
views
co-and-architecture
speedup
+1
vote
0
answers
3
Speedup in coa
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.
asked
Jan 19
in
CO and Architecture
by
Nandkishor3939
Active
(
1.3k
points)
|
103
views
pipelining
speedup
co-and-architecture
0
votes
0
answers
4
MadeEasy Test Series: CO & Architecture - Speedup
A hypothetical processor on cache read miss require one clock to send an address to MM and eight clock cycle to access a 64 bit word from MM to processor cache.miss rate of read is decreased from 14.8% to 2.6% when line size of cache is ... bz , the complete line got transfer when request of one word is made in ans key it is 4*(1+8) mentioned
asked
Jan 17
in
CO and Architecture
by
Learner_jai
Active
(
2.6k
points)
|
41
views
co-and-architecture
speedup
made-easy-test-series
+1
vote
0
answers
5
MadeEasy Test Series: CO & Architecture - Cache Memory
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to ... up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)
asked
Jan 9
in
CO and Architecture
by
Jay Bhutada 1
(
181
points)
|
123
views
made-easy-test-series
co-and-architecture
speedup
cache-memory
0
votes
2
answers
6
Speed up factor
Pipeline system has 4 stages and each stage takes 10ns. 30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up factor compare to same non pipelines, If there are 1000 instructions.
asked
Jan 1
in
CO and Architecture
by
Alina
(
9
points)
|
184
views
co-and-architecture
speedup
pipelining
0
votes
1
answer
7
ME test series
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided into 2 sub stages ... of the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825
asked
Dec 25, 2018
in
CO and Architecture
by
newdreamz a1-z0
Active
(
1.6k
points)
|
129
views
computer
co-and-architecture
pipelining
speedup
0
votes
0
answers
8
Calculate speed up ratio of pipeline
Non pipelined system takes 130ns to process an instruction . A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.
asked
Dec 21, 2018
in
CO and Architecture
by
Alina
(
9
points)
|
987
views
co-and-architecture
speedup
pipelining
0
votes
0
answers
9
Find speed up ratio
Non pipelined system takes 130 ns to process an instruction. A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.
asked
Dec 21, 2018
in
CO and Architecture
by
Alina
(
9
points)
|
88
views
co-and-architecture
speedup
0
votes
1
answer
10
gatebook COA test
Consider a program being run on a processor. A modification in processor design caused 30% of the program to speed up by ten times while three fourth of the remaining program has a speed up of 80 and 40% of the remaining part of the program performs poorer ... by 50%. The remaining program has a speedup of 1. The overall speedup of the program exact to two decimal places is:-
asked
Dec 18, 2018
in
CO and Architecture
by
sushmita
Boss
(
17.2k
points)
|
83
views
co-and-architecture
gatebook
speedup
0
votes
0
answers
11
speedup
An application program is executed on a nine-computer cluster. A benchmark program took time T on this cluster. Further, it was found that 25% of T was time in which the application was running simultaneously on all nine computers.The remaining time, the ... the percentage of code that has been parallelized (programmed or compiled so as to use the cluster mode) in the preceding program
asked
Dec 11, 2018
in
CO and Architecture
by
aambazinga
Active
(
3.4k
points)
|
82
views
co-and-architecture
speedup
william-stallings-book-question
0
votes
1
answer
12
Speed up
Consider 3 enhancements EA, EB, and EC with speedup 30, 20, 15 respectively are applied to old system to make a new system. If enhancements EA and EB are usable for 25% of the time, then the fraction (in %) of the time must EC be used to achieve an overall speed-up of 10 is ________. (in integer form)
asked
Nov 25, 2018
in
CO and Architecture
by
Shivangi Parashar 2
(
303
points)
|
171
views
co-and-architecture
speedup
0
votes
3
answers
13
Ace Test Series: CO & Architecture - SpeedUp In Pipeline
Consider a nonpipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is
asked
Nov 17, 2018
in
CO and Architecture
by
Kartavya Kothari
(
107
points)
|
317
views
pipelining
co-and-architecture
speedup
ace-test-series
0
votes
0
answers
14
SpeedUP
https://gateoverflow.in/3437/gate2007-it-6-isro2011-25 Why are they not calculating average CPI in pipelined processor and then calculating speedup ???
asked
Sep 2, 2018
in
CO and Architecture
by
daksirp
Active
(
1.6k
points)
|
27
views
speedup
cpi
0
votes
1
answer
15
Pipelining
To execute an instruction by a 32-bit machine the following steps are carried out: Fetch, Decode,Execution, Memory access and Store, each of which takes 1 clock period. In a pipelined execution of a 5-step task, a new instruction is read and ... the speedup ratio of pipe line processing system over an equivalent non pipeline processing system is ________. Ans. 4.8 Please Explain Briefly
asked
Jul 21, 2018
in
CO and Architecture
by
Na462
Loyal
(
6.9k
points)
|
189
views
pipelining
co-and-architecture
speedup
clock-cycles
0
votes
0
answers
16
WBUT 2012
A 30% enhancement in speedup for a component of the processor has been proposed for a new architecture.If the enhancement is usable only for 50% for the time,what is the fraction of the time must enhancement is used to achieve an overall speedup of 10?
asked
May 31, 2018
in
CO and Architecture
by
Sourav_35
(
171
points)
|
64
views
speedup
+2
votes
0
answers
17
Computer organization speed up
Consider a hypothetical system,which is used in application where program refers integers units and floats units.Floating units are enhanced so that they run 2 times faster,but only 90% instructions are floating point type.What isn the over all performance gain?
asked
Jan 25, 2018
in
CO and Architecture
by
rahul sharma 5
Boss
(
25.3k
points)
|
109
views
co-and-architecture
speedup
+3
votes
0
answers
18
pipelining
is it 1.92 or 1.94 i want conformation...
asked
Jan 15, 2018
in
CO and Architecture
by
pranab ray
Junior
(
779
points)
|
116
views
co-and-architecture
pipelining
speedup
+3
votes
0
answers
19
Speedup In pipelining
Actually, In this problem what will, we consider getting the answer(upper bound or lower bound) and why?
asked
Jan 13, 2018
in
CO and Architecture
by
thepeeyoosh
Active
(
2k
points)
|
202
views
pipelining
co-and-architecture
speedup
+1
vote
1
answer
20
MadeEasy Test Series: CO & Architecture - Speedup
asked
Jan 1, 2018
in
CO and Architecture
by
Kalpataru Bose
(
391
points)
|
130
views
made-easy-test-series
computer-networks
co-and-architecture
pipelining
speedup
+2
votes
1
answer
21
Pipelining
asked
Nov 29, 2017
in
CO and Architecture
by
Parshu gate
Active
(
3.1k
points)
|
150
views
pipelining
co-and-architecture
clock-cycles
speedup
0
votes
2
answers
22
Definition of Ideal Pipeline
What is the definition of an ideal pipeline? On searching over the internet I found only speed up formulas but no where the difference between ideal and non-ideal was mentioned.
asked
Nov 26, 2017
in
CO and Architecture
by
Sourajit25
Active
(
1.3k
points)
|
284
views
pipelining
co-and-architecture
speedup
+2
votes
0
answers
23
Pipelining
A 5 stage pipeline system is in operation with clock cycle of n ns. If the clock per instruction CPI for non-pipelined system is 5,and Instruction per clock for pipeline is 5,and pipeline efficiency is 70% what is the speed up factor? Please explain the Soultion and concept briefly i am little bit confused.
asked
Nov 1, 2017
in
CO and Architecture
by
Na462
Loyal
(
6.9k
points)
|
256
views
co-and-architecture
pipelining
speedup
+6
votes
1
answer
24
Pipelining Speedup
Consider a non-pipelined processor design which has a cycle time of 15ns and average CPI of 1.6. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 3ns is______________? 5 6 10 7
asked
Oct 13, 2017
in
CO and Architecture
by
akb1115
Active
(
3.3k
points)
|
839
views
pipelining
co-and-architecture
speedup
0
votes
1
answer
25
SPEEDUP CPI
. A program running on a non-pipelined processor executes 15% load instructions (5 cycles), 20% store instructions (4 cycles), 15% branch instructions (3 cycles) and 50% ALU instructions (4 cycles). What is the CPI? Now we execute this program on a ... write) in one cycle, ignoring data and control hazards (only consider structural hazards). What is the speedup over the previous one?
asked
Sep 29, 2017
in
CO and Architecture
by
Howard.xu0527
(
21
points)
|
243
views
cpi
speedup
+1
vote
0
answers
26
to solve speedup
The only instruction in the 5-stage pipelined MIPS that needs all 5 stages is Load. It has been suggested to design a 4-stage pipeline where the 4th stage will allow either a memory (read or write) operation, or a Register File write. The Load instruction ... that the two pipelines will have the same cycle time, what is the speedup of the 5-stage pipeline over the 4-stage one?
asked
Sep 29, 2017
in
CO and Architecture
by
Howard.xu0527
(
21
points)
|
160
views
co-and-architecture
pipelining
speedup
+3
votes
1
answer
27
Self Doubt In CO
Consider an instruction which has a speed up factor 12 while operating with a 70% efficiency. What could be the number of stages in the pipeline? What will be its answer 17 or 18? And why?
asked
Jul 20, 2017
in
CO and Architecture
by
Shubhanshu
Boss
(
18.2k
points)
|
119
views
co-and-architecture
pipelining
speedup
0
votes
0
answers
28
[COA[ Hamacher Problem 5.11 Find Speed up ratio
A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is initially empty. The processor fetches words from locations ... MRU policy for block replacement. The same question with LRU has been answered:- https://gateoverflow.in/11240/cache-memory
asked
May 30, 2017
in
CO and Architecture
by
rahul sharma 5
Boss
(
25.3k
points)
|
205
views
co-and-architecture
cache-memory
speedup
+8
votes
3
answers
29
Gatebook mock
asked
Feb 8, 2017
in
CO and Architecture
by
Rahul Jain25
Boss
(
11.1k
points)
|
484
views
gatebook_mt2
co-and-architecture
speedup
0
votes
1
answer
30
Number of stall cycles for given speed up
Anyone? I know my answer is wrong.
asked
Dec 12, 2016
in
CO and Architecture
by
prasitamukherjee
Active
(
2k
points)
|
121
views
stall
co-and-architecture
speedup
Page:
1
2
next »
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
-tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
Linear Algebra Important Points
GATE 2020
OFFICIAL GATE MOCK TEST RELEASED
IIITH: Winter Research Admissions 2019 (For Spring 2020)
TIFR and JEST exam
Follow @csegate
Recent questions tagged speedup
Recent Blog Comments
i also don't have any pdf, actually, I added the...
i don't have , if you have upload it
@mohan123 Do you have all standard book...
bro can be upload all standard book questions in...
it'll take 3-4 days but for most purpose you can...
50,648
questions
56,422
answers
195,194
comments
99,831
users