Recent questions tagged speedup

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0 answers

1

WBUT 2012
A 30% enhancement in speedup for a component of the processor has been proposed for a new architecture.If the enhancement is usable only for 50% for the time,what is the fraction of the time must enhancement is used to achieve an overall speedup of 10?

asked May 31 in CO & Architecture by Sourav_35 (199 points) | 28 views

+2 votes

0 answers

2

Computer organization speed up
Consider a hypothetical system,which is used in application where program refers integers units and floats units.Floating units are enhanced so that they run 2 times faster,but only 90% instructions are floating point type.What isn the over all performance gain?

asked Jan 25 in CO & Architecture by rahul sharma 5 Boss (24.1k points) | 49 views

+3 votes

0 answers

3

pipelining
is it 1.92 or 1.94 i want conformation...

asked Jan 15 in CO & Architecture by pranab ray Junior (895 points) | 55 views

+3 votes

0 answers

4

Speedup In pipelining
Actually, In this problem what will, we consider getting the answer(upper bound or lower bound) and why?

asked Jan 13 in CO & Architecture by thepeeyoosh Active (2k points) | 74 views

+2 votes

1 answer

5

Pipelining

asked Nov 29, 2017 in CO & Architecture by Parshu gate Active (4.9k points) | 65 views

0 votes

2 answers

6

Definition of Ideal Pipeline
What is the definition of an ideal pipeline? On searching over the internet I found only speed up formulas but no where the difference between ideal and non-ideal was mentioned.

asked Nov 26, 2017 in CO & Architecture by Sourajit25 Junior (791 points) | 100 views

+2 votes

0 answers

7

Pipelining
A 5 stage pipeline system is in operation with clock cycle of n ns. If the clock per instruction CPI for non-pipelined system is 5,and Instruction per clock for pipeline is 5,and pipeline efficiency is 70% what is the speed up factor? Please explain the Soultion and concept briefly i am little bit confused.

asked Nov 1, 2017 in CO & Architecture by Na462 Active (3.3k points) | 158 views

+5 votes

1 answer

8

Pipelining Speedup
Consider a non-pipelined processor design which has a cycle time of 15ns and average CPI of 1.6. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 3ns is______________? 5 6 10 7

asked Oct 13, 2017 in CO & Architecture by akb1115 Active (3.1k points) | 589 views

0 votes

1 answer

9

SPEEDUP CPI
. A program running on a non-pipelined processor executes 15% load instructions (5 cycles), 20% store instructions (4 cycles), 15% branch instructions (3 cycles) and 50% ALU instructions (4 cycles). What is the CPI? Now we execute this program on a ... write) in one cycle, ignoring data and control hazards (only consider structural hazards). What is the speedup over the previous one?

asked Sep 29, 2017 in CO & Architecture by Howard.xu0527 (37 points) | 159 views

+1 vote

0 answers

10

to solve speedup
The only instruction in the 5-stage pipelined MIPS that needs all 5 stages is Load. It has been suggested to design a 4-stage pipeline where the 4th stage will allow either a memory (read or write) operation, or a Register File write. The Load instruction ... that the two pipelines will have the same cycle time, what is the speedup of the 5-stage pipeline over the 4-stage one?

asked Sep 29, 2017 in CO & Architecture by Howard.xu0527 (37 points) | 114 views

+3 votes

1 answer

11

Self Doubt In CO
Consider an instruction which has a speed up factor 12 while operating with a 70% efficiency. What could be the number of stages in the pipeline? What will be its answer 17 or 18? And why?

asked Jul 20, 2017 in CO & Architecture by Shubhanshu Boss (15k points) | 99 views

0 votes

0 answers

12

[COA[ Hamacher Problem 5.11 Find Speed up ratio

asked May 30, 2017 in CO & Architecture by rahul sharma 5 Boss (24.1k points) | 143 views

+6 votes

3 answers

13

Gatebook mock

asked Feb 8, 2017 in CO & Architecture by Rahul Jain25 Boss (11.5k points) | 431 views

0 votes

1 answer

14

Number of stall cycles for given speed up

asked Dec 12, 2016 in CO & Architecture by prasitamukherjee Active (1.9k points) | 107 views

+1 vote

1 answer

15

Coa+ Stalls+ Speed up

asked Dec 12, 2016 in CO & Architecture by Rahul Jain25 Boss (11.5k points) | 139 views

0 votes

1 answer

16

UGCNET-Dec2012-III-49
Let $f$ be the fraction of the computation (in terms of time) that is parallelizabl$e$. $P$ the number of processors in the system, and $s_p$ the speed up achievable in comparison with sequential execution – then the $s_p$ can be calculated using the relation: $\frac{1}{1-f-f/P}$ $\frac{P}{P-f(P+1)}$ $\frac{1}{1-f+f/P}$ $\frac{P}{P+f(P-1)}$

asked Jul 13, 2016 in CO & Architecture by jothee Veteran (98.5k points) | 272 views

0 votes

2 answers

17

Made Easy Test Series

asked Dec 17, 2015 in CO & Architecture by sonu Active (2.3k points) | 155 views

+3 votes

1 answer

18

Pipeline q 18 CA
A nonpipeline system takes 50 ns to process a task. The same task can be processed in a six segment pipeline with a clock cycle of 10 ns. determine the speed up ratio of the pipeline for 100 tasks. a. 3.76 b. 4.76 c. 5.76 d. 2.76

asked Oct 20, 2015 in CO & Architecture by khushtak Loyal (7.6k points) | 2.2k views

+2 votes

3 answers

19

Made easy CA q17
The time delays of 4 segments are 60 ns, 70 ns, 100 ns and 80 ns respectively. Interface registers are have the delay of 10 ns. what is the speed up? a. 2.9 b. 2.6 c. 3.2 d. 1.8

asked Oct 20, 2015 in CO & Architecture by khushtak Loyal (7.6k points) | 738 views

+19 votes

4 answers

20

GATE2014-1-55
Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes 25% less time but incurs 20% more CPI (clock cycles per instruction) as compared to the program running on $P_1$. If the clock frequency of $P_1$ is 1GHZ, then the clock frequency of $P_2$ (in GHz) is ______.

asked Sep 28, 2014 in CO & Architecture by jothee Veteran (98.5k points) | 3.5k views

+21 votes

8 answers

21

GATE2004-IT-50
In an enhancement of a design of a CPU, the speed of a floating point until has been increased by 20% and the speed of a fixed point unit has been increased by 10%. What is the overall speedup achieved if the ratio of the number of floating point operations to ... operation used to take twice the time taken by the fixed point operation in the original design? 1.155 1.185 1.255 1.285

asked Sep 15, 2014 in CO & Architecture by gatecse Boss (18k points) | 3.7k views

tags	tag:apple
author	user:martin
title	title:apple
content	content:apple
exclude	-tag:apple
force match	+apple
views	views:100
score	score:10
answers	answers:2
is accepted	isaccepted:true
is closed	isclosed:true

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