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Recent questions tagged speedup

1 vote
3 answers
1
A nonpipeline system taken $50ns$ to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of $10ns.$ Determinant the speedup ration of the pipeline for $100$ tasks. What is the maximum speedup that can be achieved? $4.90,5$ $4.76,5$ $3.90,5$ $4.30,5$
asked Mar 31 in CO and Architecture Lakshman Patel RJIT 181 views
0 votes
0 answers
3
1 vote
0 answers
4
In a processor each instruction execution completes in 4 clock cycle with 2.5 gigahertz. The same processor is transformed into a pipelined processor with five stages operated with 2.0 gigahertz what is the speedup achieved.
asked Jan 19, 2019 in CO and Architecture Nandkishor3939 252 views
0 votes
0 answers
5
A hypothetical processor on cache read miss require one clock to send an address to MM and eight clock cycle to access a 64 bit word from MM to processor cache.miss rate of read is decreased from 14.8% to 2.6% when line size of cache is increased from one word to four ... ] will be required bz , the complete line got transfer when request of one word is made in ans key it is 4*(1+8) mentioned
asked Jan 17, 2019 in CO and Architecture Learner_jai 74 views
1 vote
1 answer
6
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache is ... four words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is (Upto 2 decimal places)
asked Jan 9, 2019 in CO and Architecture Jay Bhutada 1 231 views
0 votes
2 answers
7
Pipeline system has 4 stages and each stage takes 10ns. 30% instructions are branch instructions .each branch instruction introduces delay of 3 cycle. What is speed up factor compare to same non pipelines, If there are 1000 instructions.
asked Jan 1, 2019 in CO and Architecture Alina 430 views
1 vote
1 answer
8
Consider a pipeline 'x', consist of 5 stages named as IF, ID, OF, EX and WB with the respective stage delays of 2 ns, 6 ns, 5 ns, 8 ns and 1 ns. The alternative pipeline 'y' contain the same number of stages but EX stage is divided into 2 sub stages, (EX1 and ... 20% of the instructions which are memory based instructions, what is the ratio of speedup of x to speedup of y? 0.727 0.902 0.665 0.825
asked Dec 25, 2018 in CO and Architecture newdreamz a1-z0 227 views
0 votes
0 answers
9
Non pipelined system takes 130ns to process an instruction . A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.
asked Dec 21, 2018 in CO and Architecture Alina 2.7k views
0 votes
0 answers
10
Non pipelined system takes 130 ns to process an instruction. A program of 1000 instructions is executed in non pipelined system. Then same program is processed with processor with 5 segment pipeline with clock cycle of 30 ns/stage. Determine speed up ratio of pipeline.
asked Dec 21, 2018 in CO and Architecture Alina 194 views
2 votes
3 answers
11
Consider a program being run on a processor. A modification in processor design caused 30% of the program to speed up by ten times while three fourth of the remaining program has a speed up of 80 and 40% of the remaining part of the program performs poorer and looses its speed by 50%. The remaining program has a speedup of 1. The overall speedup of the program exact to two decimal places is:—
asked Dec 18, 2018 in CO and Architecture sushmita 167 views
1 vote
0 answers
12
An application program is executed on a nine-computer cluster. A benchmark program took time T on this cluster. Further, it was found that 25% of T was time in which the application was running simultaneously on all nine computers.The remaining time, the ... the percentage of code that has been parallelized (programmed or compiled so as to use the cluster mode) in the preceding program
asked Dec 11, 2018 in CO and Architecture aambazinga 200 views
0 votes
1 answer
13
Consider 3 enhancements EA, EB, and EC with speedup 30, 20, 15 respectively are applied to old system to make a new system. If enhancements EA and EB are usable for 25% of the time, then the fraction (in %) of the time must EC be used to achieve an overall speed-up of 10 is ________. (in integer form)
asked Nov 25, 2018 in CO and Architecture Shivangi Parashar 2 371 views
1 vote
4 answers
14
Consider a non­pipelined processor design which has a cycle time of 10ns and average CPI of 1.4. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 2ns is
asked Nov 17, 2018 in CO and Architecture Kartavya Kothari 435 views
0 votes
0 answers
15
https://gateoverflow.in/3437/gate2007-it-6-isro2011-25 Why are they not calculating average CPI in pipelined processor and then calculating speedup ???
asked Sep 2, 2018 in CO and Architecture daksirp 83 views
0 votes
1 answer
16
To execute an instruction by a 32-bit machine the following steps are carried out: Fetch, Decode,Execution, Memory access and Store, each of which takes 1 clock period. In a pipelined execution of a 5-step task, a new instruction is read and it takes ... the speedup ratio of pipe line processing system over an equivalent non pipeline processing system is ________. Ans. 4.8 Please Explain Briefly
asked Jul 21, 2018 in CO and Architecture Na462 508 views
0 votes
0 answers
17
A 30% enhancement in speedup for a component of the processor has been proposed for a new architecture.If the enhancement is usable only for 50% for the time,what is the fraction of the time must enhancement is used to achieve an overall speedup of 10?
asked May 31, 2018 in CO and Architecture Sourav_35 330 views
2 votes
0 answers
18
Consider a hypothetical system,which is used in application where program refers integers units and floats units.Floating units are enhanced so that they run 2 times faster,but only 90% instructions are floating point type.What isn the over all performance gain?
asked Jan 25, 2018 in CO and Architecture rahul sharma 5 161 views
3 votes
1 answer
19
is it 1.92 or 1.94 i want conformation...
asked Jan 15, 2018 in CO and Architecture pranab ray 154 views
3 votes
0 answers
20
Actually, In this problem what will, we consider getting the answer(upper bound or lower bound) and why?
asked Jan 13, 2018 in CO and Architecture thepeeyoosh 265 views
2 votes
1 answer
22
0 votes
2 answers
23
What is the definition of an ideal pipeline? On searching over the internet I found only speed up formulas but no where the difference between ideal and non-ideal was mentioned.
asked Nov 26, 2017 in CO and Architecture Sourajit25 609 views
3 votes
1 answer
24
A 5 stage pipeline system is in operation with clock cycle of n ns. If the clock per instruction CPI for non-pipelined system is 5,and Instruction per clock for pipeline is 5,and pipeline efficiency is 70% what is the speed up factor? Please explain the Soultion and concept briefly i am little bit confused.
asked Nov 1, 2017 in CO and Architecture Na462 421 views
7 votes
1 answer
25
Consider a non-pipelined processor design which has a cycle time of 15ns and average CPI of 1.6. The maximum speedup pipelined processor can get by pipelining it into 5 stages and each stage takes 3ns is______________? 5 6 10 7
asked Oct 13, 2017 in CO and Architecture akb1115 949 views
1 vote
0 answers
26
Consider the example in Section $2.5$ for the calculation of average CPI and MIPS rate, which yielded the result of CPI $2.24$ and MIPS rate $178$. Now assume that the program can be executed in eight parallel tasks or threads with roughly equal number ... factor. d. Compare the actual speedup factor with the theoretical speedup factor determined by Amdhal's law. someone please explain the part d.
asked Oct 9, 2017 in CO and Architecture arch 204 views
0 votes
1 answer
27
. A program running on a non-pipelined processor executes 15% load instructions (5 cycles), 20% store instructions (4 cycles), 15% branch instructions (3 cycles) and 50% ALU instructions (4 cycles). What is the CPI? Now we execute this program on a 5-stage ... (or write) in one cycle, ignoring data and control hazards (only consider structural hazards). What is the speedup over the previous one?
asked Sep 29, 2017 in CO and Architecture Howard.xu0527 445 views
2 votes
1 answer
28
The only instruction in the 5-stage pipelined MIPS that needs all 5 stages is Load. It has been suggested to design a 4-stage pipeline where the 4th stage will allow either a memory (read or write) operation, or a Register File write. The Load instruction will then ... assuming that the two pipelines will have the same cycle time, what is the speedup of the 5-stage pipeline over the 4-stage one?
asked Sep 29, 2017 in CO and Architecture Howard.xu0527 235 views
3 votes
1 answer
29
Consider an instruction which has a speed up factor 12 while operating with a 70% efficiency. What could be the number of stages in the pipeline? What will be its answer 17 or 18? And why?
asked Jul 20, 2017 in CO and Architecture Shubhanshu 147 views
0 votes
0 answers
30
A computer system contains a main memory of 32K 16-bit words. It also has a 4Kword cache divided into four-line sets with 64 words per line. Assume that the cache is initially empty. The processor fetches words from locations 0, 1, 2, . . ., 4351 in ... the cache. Assume an MRU policy for block replacement. The same question with LRU has been answered:- https://gateoverflow.in/11240/cache-memory
asked May 30, 2017 in CO and Architecture rahul sharma 5 267 views
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