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Recent questions tagged speedup
4
votes
3
answers
61
Test by Bikram | Mock GATE | Test 1 | Question: 49
Consider two machines, machine $A$ and machine $B$. Machine $B$ runs floating-point instructions $n$ times faster than machine $A$. Consider a program that takes $100$ $seconds$ to run on machine $A$, and spends half of its time in ... $A$) then the value of $n$ is _________ (In case of fractional value of $n$ give nearest higher positive integer).
Consider two machines, machine $A$ and machine $B$. Machine $B$ runs floating-point instructions $n$ times faster than machine $A$.Consider a program that takes $100$ $se...
Bikram
1.4k
views
Bikram
asked
Jan 16, 2017
GATE
tbb-mockgate-1
numerical-answers
speedup
co-and-architecture
+
–
2
votes
2
answers
62
Floating point
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 30% and the speed of a fixed point unit has been increased by 20%. The overall speedup achieved if the ratio of the number of fixed point operation ... point operation used to take twice the time taken by fixed point operation in the original design (upto 2 decimal places) is _________.
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 30% and the speed of a fixed point unit has been increased by 20%. The ov...
srestha
998
views
srestha
asked
Jan 5, 2017
CO and Architecture
co-and-architecture
speedup
+
–
0
votes
1
answer
63
Number of stall cycles for given speed up
Anyone? I know my answer is wrong.
Anyone? I know my answer is wrong.
prasitamukherjee
470
views
prasitamukherjee
asked
Dec 12, 2016
CO and Architecture
stall
co-and-architecture
speedup
+
–
1
votes
1
answer
64
Coa+ Stalls+ Speed up
Rahul Jain25
795
views
Rahul Jain25
asked
Dec 11, 2016
CO and Architecture
co-and-architecture
cache-memory
stall
speedup
+
–
1
votes
1
answer
65
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 24
Consider two pipelines A and B. Pipeline A has $8$ stages with uniform stage delay of $2$ns. Pipeline B has $5$ stages with uniform stage delays of $3$ns. Time saved (in ns) by pipeline A compared to pipeline B to execute $100$ instructions is _____.
Consider two pipelines A and B. Pipeline A has $8$ stages with uniform stage delay of $2$ns. Pipeline B has $5$ stages with uniform stage delays of $3$ns. Time saved (in ...
Bikram
294
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
pipelining
speedup
+
–
3
votes
1
answer
66
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 16
A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots $85$ % of the time, and can fill the second slot only $20$ % of the time. ... the instructions executed are branch instructions, then the percentage improvement in performance achieved by this optimization is ________%.
A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots $85$ % of the time, and can fill the second slot only $20$ % of the t...
Bikram
1.4k
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
pipelining
speedup
numerical-answers
+
–
0
votes
2
answers
67
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 13
A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns. The speed-up rotation of the pipeline for $10$ tasks will be _______.
A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns.The speed-up rotation of the p...
Bikram
348
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
pipelining
speedup
numerical-answers
+
–
1
votes
1
answer
68
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 1
We have two implementations of the same Instruction Set Architecture (ISA). Machine $A$ has a clock cycle time of $50$ ns and a CPI of $4.0$ for a program, while machine $B$ has a clock cycle of $65$ ns and a ... is TRUE? Machine A is faster than B. Machine B is faster than A. Both have the same speed. None of the above
We have two implementations of the same Instruction Set Architecture (ISA). Machine $A$ has a clock cycle time of $50$ ns and a CPI of $4.0$ for a program, while machine ...
Bikram
369
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
speedup
+
–
0
votes
1
answer
69
UGC NET CSE | December 2012 | Part 3 | Question: 49
Let $f$ be the fraction of the computation (in terms of time) that is parallelizabl$e$. $P$ the number of processors in the system, and $s_p$ the speed up achievable in comparison with sequential execution – then the $s_p$ can be calculated using the relation: $\frac{1}{1-f-f/P}$ $\frac{P}{P-f(P+1)}$ $\frac{1}{1-f+f/P}$ $\frac{P}{P+f(P-1)}$
Let $f$ be the fraction of the computation (in terms of time) that is parallelizabl$e$. $P$ the number of processors in the system, and $s_p$ the speed up achievable in c...
go_editor
2.1k
views
go_editor
asked
Jul 13, 2016
CO and Architecture
ugcnetcse-dec2012-paper3
co-and-architecture
speedup
+
–
1
votes
2
answers
70
MadeEasy Test Series: CO & Architecture - Pipelining
Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being branch. The value of X such that speedup is atleast 5 is ________ ? ------------ ... 5 => 1200 = 1040 - 15X => 15X = - 160 Which is not possible. Where am I going wrong ?? :
Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being b...
Tushar Shinde
1.1k
views
Tushar Shinde
asked
Jan 14, 2016
CO and Architecture
made-easy-test-series
co-and-architecture
pipelining
speedup
+
–
0
votes
3
answers
71
MadeEasy Test Series: CO & Architecture - Speedup
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 30% and the speed of a fixed point unit has been increased by $20$%. The overall speedup achieved if the ratio of the ... operation used to take twice the time taken by fixed point operation in the original design(upto $2$ decimal places is __________.
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by 30% and the speed of a fixed point unit has been increased by $20$%. The ...
sonu
575
views
sonu
asked
Dec 17, 2015
CO and Architecture
speedup
co-and-architecture
made-easy-test-series
+
–
3
votes
1
answer
72
Pipeline q 18 CA
A nonpipeline system takes 50 ns to process a task. The same task can be processed in a six segment pipeline with a clock cycle of 10 ns. determine the speed up ratio of the pipeline for 100 tasks. a. 3.76 b. 4.76 c. 5.76 d. 2.76
A nonpipeline system takes 50 ns to process a task. The same task can be processed in a six segment pipeline with a clock cycle of 10 ns. determine the speed up ratio o...
khushtak
13.5k
views
khushtak
asked
Oct 19, 2015
CO and Architecture
co-and-architecture
pipelining
speedup
+
–
2
votes
3
answers
73
Made easy CA q17
The time delays of 4 segments are 60 ns, 70 ns, 100 ns and 80 ns respectively. Interface registers are have the delay of 10 ns. what is the speed up? a. 2.9 b. 2.6 c. 3.2 d. 1.8
The time delays of 4 segments are 60 ns, 70 ns, 100 ns and 80 ns respectively. Interface registers are have the delay of 10 ns. what is the speed up?a. 2.9 ...
khushtak
5.3k
views
khushtak
asked
Oct 19, 2015
CO and Architecture
co-and-architecture
pipelining
speedup
+
–
49
votes
7
answers
74
GATE CSE 2014 Set 1 | Question: 55
Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes $\text{25%}$ less time but incurs $\text{20%}$ more CPI (clock cycles per instruction) ... If the clock frequency of $P_1$ is $\text{1GHZ}$, then the clock frequency of $P_2$ (in GHz) is ______.
Consider two processors $P_1$ and $P_2$ executing the same instruction set. Assume that under identical conditions, for the same input, a program running on $P_2$ takes $...
go_editor
18.1k
views
go_editor
asked
Sep 28, 2014
CO and Architecture
gatecse-2014-set1
co-and-architecture
numerical-answers
normal
speedup
+
–
43
votes
11
answers
75
GATE IT 2004 | Question: 50
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by $\text{20%}$ and the speed of a fixed point unit has been increased by $\text{10%}$. What is the overall speedup achieved if the ratio of the number of ... to take twice the time taken by the fixed point operation in the original design? $1.155$ $1.185$ $1.255$ $1.285$
In an enhancement of a design of a CPU, the speed of a floating point unit has been increased by $\text{20%}$ and the speed of a fixed point unit has been increased by $\...
gatecse
19.0k
views
gatecse
asked
Sep 15, 2014
CO and Architecture
gateit-2004
normal
co-and-architecture
speedup
+
–
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