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Recent questions tagged stall

11 votes

4 answers

1

GATE CSE 2022 | Question: 51
A processor $\text{X}_{1}$ operating at $2 \; \text{GHz}$ has a standard $5-$stage $\text{RISC}$ instruction pipeline having a base $\text{CPI (cycles per instruction)}$ of one without any pipeline hazards. For a given program $\text{P}$ ... $\text{X}_{2}$ over $\text{X}_{1}$ in executing $\text{P}$ is _______________.

Arjun asked in CO and Architecture Feb 15, 2022

by Arjun

3.6k views

4 votes

0 answers

2

#pipeline #self doubt
Consider a 5—stage pipeline processor used to execute 200 number of instructions and among those 100 instructions cause 3 stall cycles each. What is the total cycles required for these operation if CPI is not equal to one.

jayadev asked in CO and Architecture Feb 3, 2022

264 views

0 votes

0 answers

3

PIPELINING.
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?

Ritabrata Dey asked in CO and Architecture May 21, 2019

by Ritabrata Dey

288 views

0 votes

0 answers

4

#Pipeliningdoubt
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.

Ritabrata Dey asked in CO and Architecture Apr 16, 2019

by Ritabrata Dey

136 views

0 votes

1 answer

5

How many stall cycles are caused due to each incorrect branch prediction?
The title says it all: How many stall cycles are caused due to each incorrect branch prediction? Additional details you might need: Branch is executed in execution stage of pipeline (but will love to know what happens when branch is executed in decode stage too)

Raj Singh 1 asked in CO and Architecture Jan 9, 2019

576 views

2 votes

1 answer

6

Average memory stall
Consider a CPU contains 2000 instructions, there are 80 misses in L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit ... .8 memory references per instruction, then average stall per instruction is ________. Can you please suggest the method to attempt such questions.

Shamim Ahmed asked in CO and Architecture Dec 22, 2018

by Shamim Ahmed

908 views

0 votes

2 answers

7

ME Test Series
Consider a CPU containing 2000 instructions, there are 80 misses In the $L_1$ cache and 40 misses In the $L_2$ cache. Assume the miss penalty from the $L_2$ cache to memory is 200 clock cycles, the hit time of $L_2$ cache Is 30 clock cycles, ... time of $L_1$ cache Is 5 clock cycles and these are 1.8 memory references per instruction, then average stall per instruction Is _________.

Shadan Karim asked in CO and Architecture Nov 24, 2018

by Shadan Karim

378 views

0 votes

0 answers

8

pipeline
consider a5 stage pipeline processor, 20% load instructions, 25% branches, 20% stores, 20% of all instructions are data dependent on instructions in front of them and branches are taken 75%of time. what would be the expected cpi?

rishabhdevsingh1 asked in CO and Architecture Nov 10, 2018

by rishabhdevsingh1

481 views

0 votes

1 answer

9

Clock per instruction
What is the difference between Effective CPI and Average CPI ? A program is run on 40 MHZ with instruction mix and corresponding clock cycle count. Determine : * Effective CPI * Average CPI Instruction Clock Cycle Instruction Count Arithmetic 1 45000 Floating Point 2 32000 Data Transfer 2 15000 Control Transfer 2 8000

Na462 asked in CO and Architecture Oct 12, 2018

by Na462

781 views

0 votes

1 answer

10

Branch prediction in pipelining part of syllabhs?
Is branch prediction in pipelining im Co and architecture part of gate syllabus?

bts1jimin asked in CO and Architecture Oct 3, 2018

401 views

0 votes

0 answers

11

Shiv Gaur asked in CO and Architecture Sep 13, 2018

91 views

0 votes

1 answer

12

Pipeline Doubt
Its a snapshot from hamacher. According to me there should be stall of 2 cycles why 3 ?? Because after Write stage the data will be available in register file so why extra stall in 6th clock cycle ?

Na462 asked in CO and Architecture Sep 3, 2018

by Na462

510 views

1 vote

1 answer

13

COA -INSTRUCTION PIPELINE
Consider a 4 stage pipeline:fetch-IF(2cycle), decode& read -ID(1 cycle) execute-Ex(4 cycle for multiply and 7 cycle for divide ,1 cycle for all other arithmatic operations ) and Write Back WB(1 cycle) . Assume that in a program A there ... divides,85% of othe types of instructions that take 1 cycle in execute stage . How many cycle does it take to execute program A?

gourav94240 asked in CO and Architecture Aug 28, 2018

503 views

0 votes

1 answer

14

Pipeline
A computer with a 5 stage pipeline deals with conditional branches by stalling for the next 3 cycle after hitting one. how much does stalling hurt the performance is 20% of all instructions are conditional branches.

Jaggi asked in CO and Architecture Jul 7, 2018

by Jaggi

734 views

0 votes

0 answers

15

Branch Stall
What does the Following line states:- Branch instruction aren't overlapped i.e. the instruction after the branch is not fetched till the branch instruction is executed. Say in below Question :- An instruction pipeline has Five Stages where each stage takes 2ns ... fetching the branch target the instruction which was incorrectly fetched will be in stage 4. Hence total 4 Stalls isn't it?

Na462 asked in CO and Architecture Apr 28, 2018

by Na462

377 views

3 votes

1 answer

16

Pipeline Stall
Whenever Question is given on pipeline with branching i am confused to calculate that how many stalls will be there in the pipeline according to the constraint depicted in the pipeline. How to solve Such Questions? Like in this Question https://gateoverflow.in/683/gate2000 ... And what is meant by this line "If there are N Cycles then N-1 Stalls will be there"? Please Help

Na462 asked in CO and Architecture Apr 19, 2018

by Na462

1.8k views

0 votes

0 answers

17

Pipeline
Meaning of stall per cycle. Explain briefly

RAM CHANDRA SAHU asked in CO and Architecture Mar 17, 2018

by RAM CHANDRA SAHU

141 views

0 votes

1 answer

18

Pipeline Stall
I am very Confused in determining the number of stalls in a given execution. Please determine how to find out the number of stalls in the execution of the pipeline. Like In this example calculate the number of stalls:- I successfully calculated the total clock cycle but plz indicate number of ... place ? Instruction Fetch Decode Execute Write 1 1 2 2 1 2 2 3 3 2 3 3 1 1 1 4 1 1 1 1

Na462 asked in CO and Architecture Mar 16, 2018

by Na462

640 views

0 votes

0 answers

19

Pipeline Stalls
I am very Confused to how to calculate Delay SLOTS in a given Pipeline. Can anybody explain the technique for finding the number of delay slots and Stalls in A pipelined processor. 2. Is delay slot and pipeline stall the same thing. Because delay slot is created using branch ... - --- I4 = F D E M W So 3 stalls right? what about Pipeline stalls?? Plz explain where i am wrong?

Na462 asked in CO and Architecture Mar 13, 2018

by Na462

417 views

3 votes

2 answers

20

Average Number of stalls
Consider a CPU contains 2000 instructions, there are 80 misses in the L1 cache and 40 misses in the L2 cache. Assume miss penalty from the L2 cache to memory is 200 clock cycles, the hit time of L2 cache is 30 clock cycles, the hit time of L1 cache is 5 clock cycles and ... 0.95 * 0 {As there is no stalls when hit in L1 cache} + 0.05(30 + 0.5 * 200) 6.5 stalls/instruction.

Shubhanshu asked in CO and Architecture Jan 8, 2018

777 views

8 votes

4 answers

21

Avg stall cycles per instruction
Suppose that in $500$ memory references there are $50$ misses in the first level cache and $20$ misses in second level cache. Assume miss penalty from the $L_{2}$ cache to memory is $100$ cycles. The hit time of $L_{2}$ cache is $20$ ... $L_{1}$ cache is $10$ cycles. If there are $2.5$ memory references per instruction. How many average stall cycle per instruction?

Parshu gate asked in CO and Architecture Dec 25, 2017

3.5k views

0 votes

1 answer

22

COA:- Average stalls per instruction
What will be L1 miss rate? I think it is 80/3600 ,but then answer did not match. But if i take 80/2000,then it matches with the given answer

rahul sharma 5 asked in CO and Architecture Nov 6, 2017

by rahul sharma 5

636 views

1 vote

1 answer

23

Number of stall cycles in case of branch misprediction
Consider that branch outcomes are determined in the EX stage and the pipeline uses some prediction mechanism. If the misprediction happens, how many stall cycles gets introduced per mispredicted branch instruction?

GateAspirant999 asked in CO and Architecture Jul 9, 2017

by GateAspirant999

419 views

5 votes

1 answer

24

COA pipeline doubt
I) In a 4 stage pipeline processor, if each stage takes 4 cycles then what is CPI in case of successfull pipeline??? II) In a 4 stage pipeline processor, if each stage takes 2,3,4,5 cycles respectively then what is CPI in case ... are branch imstructions and branch address is available in 3rd stage then what should be branch pelanty??(In both the implementations mentioned above)

Rahul Jain25 asked in CO and Architecture Feb 5, 2017

by Rahul Jain25

666 views

4 votes

2 answers

25

Pipeline
Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being branch. The value of X such that speedup is atleast 5 is?

Prajwal Bhat asked in CO and Architecture Jan 22, 2017

by Prajwal Bhat

1.7k views

5 votes

3 answers

26

CO Cache stall cycles
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory is 100 cycles.The hit time of L2 cache is 20 cycle.The hit time of the L1 cache is 10 cycles. If there are 2.5 memory references per instruction.How many average stall cycles per instructions are there?

Prajwal Bhat asked in CO and Architecture Jan 7, 2017

by Prajwal Bhat

3.2k views

0 votes

1 answer

27

Number of stall cycles for given speed up
Anyone? I know my answer is wrong.

prasitamukherjee asked in CO and Architecture Dec 12, 2016

by prasitamukherjee

327 views

1 vote

1 answer

28

Coa+ Stalls+ Speed up

Rahul Jain25 asked in CO and Architecture Dec 12, 2016

by Rahul Jain25

482 views

1 vote

1 answer

29

Stall Cycles-Without Forwarding
anyone elaborate the reason for each stall cycles.

Shashank Chandekar asked in CO and Architecture Oct 26, 2016

by Shashank Chandekar

1.4k views

2 votes

1 answer

30

stall
lw $R2,100($R5) sw $R2,200($R6)............ with out any bypass paths how many cycles does the sw instruction.. need to stall for? 5 stage pipeline

monty asked in CO and Architecture Nov 24, 2015

by monty

331 views

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Recent questions tagged stall