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Recent questions tagged synchronousasynchronouscircuits
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Synchronous Counter Circuit
In the given synchronous Counter circuit, initially all Outputs are Reset. It is required to replace FF2 with AB Flip Flop. The FF2 inputs would be: A. A = Q1 and B = Q1' B. A = Q1' and B = Q1' C. A = Q1.Q0 and B = Q1.Q0 D. A = Qo' and B = Qo'
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Oct 10
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Na462
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digitallogic
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digitalcounter
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Synchronous Counter
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Digital Logic
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virtual gate
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Nov 13, 2017
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Digital Logic
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virtualgate
synchronousasynchronouscircuits
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MadeEasy Test
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of MOD 256 counter ?(in MHz) a)18.18 b)19.18 c)20.19 d)17.18 I am not ... 30 nsec which makes Frequency = 1/(30 nsec) = 33.33 Mhz? please correct me where I am going wrong. Thanks for your help :)
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Oct 10, 2017
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Digital Logic
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Kamal Pratap
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madeeasytestseries
digitallogic
synchronousasynchronouscircuits
clockfrequency
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5
doubt synchronous counter
what is the correct way to design synchronous counter ?for any arbitrary sequence like 7,3,1,2,5,4,6,7,3,1,2,4,5,6 I simply using state table diagram and by minimization it is easy to design circuit.Also to identify minimum number ... flop in synchronous counter I just calculating number of bits used in counter . pls tell correct approach to solve these type of problems
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Oct 2, 2017
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Digital Logic
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set2018
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58
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digitallogic
synchronousasynchronouscircuits
selfdoubt
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6
gate 2014
which is faster, synchronous circuits or asynchronous circuits and why?
asked
Aug 29, 2017
in
Digital Logic
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Sunil8860
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131
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196
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digitallogic
synchronousasynchronouscircuits
asynchronouscircuit
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7
made easy test series
If the Initial state $(Q_{2}\,Q_{1}\,Q_{0})$ of the counter is $101$,then the state $(Q_{2}\,Q_{1}\,Q_{0})$ after $4$ clock pulses is
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Jan 31, 2017
in
Digital Logic
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naveen81
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139
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madeeasytestseries
digitallogic
synchronousasynchronouscircuits
digitalcounter
+13
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2
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8
GATE199816
Design a synchronous counter to go through the following states: $$1, 4, 2, 3, 1, 4, 2, 3, 1, 4 \dots $$
asked
Sep 26, 2014
in
Digital Logic
by
Kathleen
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762
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gate1998
digitallogic
normal
descriptive
synchronousasynchronouscircuits
+20
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4
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9
GATE200344
A $\text{1input}$, $\text{2output}$ synchronous sequential circuit behaves as follows: Let $z_k, n_k$ denote the number of $0'$s and $1's$ respectively in initial k bits of the input $(z_k+n_k=k)$. The circuit outputs $00$ until one of the ... clock ticks is $01$. What is the minimum number of states required in the state transition graph of the above circuit? $5$ $6$ $7$ $8$
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Sep 17, 2014
in
Digital Logic
by
Kathleen
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2.7k
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gate2003
digitallogic
synchronousasynchronouscircuits
normal
+17
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3
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10
GATE20012.12
Consider the circuit given below with initial state $Q_0=1, Q_1=Q_2=0$. The state of the circuit is given by the value $4Q_2+2Q_1+Q_0$ Which one of the following is correct state sequence of the circuit? $1, 3, 4, 6, 7, 5, 2$ $1, 2, 5, 3, 7, 6, 4$ $1, 2, 7, 3, 5, 6, 4$ $1, 6, 5, 7, 2, 3, 4$
asked
Sep 15, 2014
in
Digital Logic
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Kathleen
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gate2001
digitallogic
normal
synchronousasynchronouscircuits
+12
votes
2
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11
GATE199103ii
Choose the correct alternatives (more than one may be correct) and write the corresponding letters only: Advantage of synchronous sequential circuits over asynchronous ones is: faster operation ease of avoiding problems due to hazards lower hardware requirement better noise immunity none of the above
asked
Sep 12, 2014
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Digital Logic
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Kathleen
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gate1991
digitallogic
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synchronousasynchronouscircuits
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