The Gateway to Computer Science Excellence
For all GATE CSE Questions
Toggle navigation
GATE Overflow
Facebook Login
or
Email or Username
Password
Remember
Login
Register

I forgot my password
Activity
Questions
Unanswered
Tags
Subjects
Users
Ask
Prev
Blogs
New Blog
Exams
First time here? Checkout the
FAQ
!
x
×
Close
Use the google search bar on side panel. It searches through all previous GATE/other questions. For hardcopy of previous year questions please see
here
Recent questions tagged synchronousasynchronouscircuits
0
votes
0
answers
1
Morris Mano Edition 3 Exercise 9 Question 24 (Page No. 396)
The boolean functions for the input of SR latch are as follows. Obtain the circuit diagram using a minimum number of NAND gates. $S = x _1’x _2’x _3 + x _1x _2x _3$. $R = x _1x _2’ + x _2x _3’$
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

15
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
minnogates
0
votes
0
answers
2
Morris Mano Edition 3 Exercise 9 Question 23 (Page No. 396)
Draw the logic diagram of the product of sum expression $ Y = (x _1 + x _2’)(x _2 + x _3)$ Show that there is a static 0 hazard when $x _1$ and $x _3$ is equal to zero and $x _2$ goes from 0 to 1.Find a way to remove hazard by adding one more OR gate.
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

4
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
hazards
0
votes
0
answers
3
Morris Mano Edition 3 Exercise 9 Question 22 (Page No. 396)
Find a circuit that has no static hazard and implements the boolean function: F(A,B,C,D) = $\sum(0,2,6,7,8,10,12)$
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

6
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
hazards
0
votes
0
answers
4
Morris Mano Edition 3 Exercise 9 Question 18 (Page No. 395)
Merge each of the primitive flow table shown in the figure. Proceed as follows: Find all compatible pairs by means of implication table. Find the maximal compatibles by means of a merger diagram FInd the minimal set of compatibles that covers all the states and is closed.
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

16
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
5
Morris Mano Edition 3 Exercise 9 Question 17 (Page No. 395)
Reduce the number of states in the state table listed below. Use an implication table.
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

11
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
6
Morris Mano Edition 3 Exercise 9 Question 16 (Page No. 395)
Using the implication table method, show that the state table listed in the figure cannot be reduced any further.
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

11
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
7
Morris Mano Edition 3 Exercise 9 Question 15 (Page No. 395)
Assign output values to the don’t care states in the flow tables in the figure below in such a way as to avoid transient output places
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

6
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
8
Morris Mano Edition 3 Exercise 9 Question 14 (Page No. 394)
It is necessary to design an asynchronous sequential circuit with two inputs, $x _1 and x _2$, and one output $z$. Initially, both input and output are zero. when $x _1 and x _2$ becomes 1, z becomes 1. when the ... for the circuit and show that it can be reduced to the flow table shown in the figure complete the design of the circuit.
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

7
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
9
Morris Mano Edition 3 Exercise 9 Question 13,25 (Page No. 394)
A traffic light is installed at the junction of the railroad and a road. The traffic light is controlled by two switches in the rails placed one mile apart on either side of the junction. A switch is turned on when a ... circuit. show that the flow table can be reduced to four rows Complete the circuit specified in the above problem.
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

9
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
10
Morris Mano Edition 3 Exercise 9 Question 12 (Page No. 394)
Obtain a primitive flow table for a circuit with two inputs, $x _1 and x _2$ and two outputs $y _1 and y _2$, that satisfy the following four conditions. When $x _1x _2 = 00$, the output is $z _1z _2 = 00$. when $x _1 = 1$ and ... $x _1$ changes from 0 to 1, the output is $z _1z _2$ = 10. otherwise the output does not change.
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

3
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
11
Morris Mano Edition 3 Exercise 9 Question 11 (Page No. 394)
Implement the circuit defined below with NAND SR latch. An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows. $Y _1 = x _1x _2 + x _1y _2’ + x _2’y _1$ $Y _2 = x _2 + x _1y _1’y _2 + x _1’y _1$ $z = x _2 + y _1$
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

4
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
latch
0
votes
0
answers
12
Morris Mano Edition 3 Exercise 9 Question 10 (Page No. 394)
Implement the circuit with defined below with NOR SR latch. an asynchronous circuit is described by the following excitation and output functions: $Y = x _1x _2’ + (x _1 + x _2’)y$ $z = y$
asked
Apr 8
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

7
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
latch
0
votes
0
answers
13
Morris Mano Edition 3 Exercise 9 Question 9 (Page No. 394)
For the asynchronous sequential circuit shown in the figure: Derive the boolean functions for the outputs of two SR latches $Y _1 and Y _2$. Note that the S input of the second latch is $x _1’y _1’$. Derive the transition table and output map of the circuit.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

7
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
latch
flipflop
0
votes
0
answers
14
Morris Mano Edition 3 Exercise 9 Question 8 (Page No. 394)
Convert the circuit of the figure to the asynchronous sequential circuit by removing the clockpulse(CP) and changes the flipflops to the SR latches. Derive the transition table and output map of the modified circuit.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

6
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
flipflop
0
votes
0
answers
15
Morris Mano Edition 3 Exercise 9 Question 7 (Page No. 394)
Analyze the T flipflop shown in the figure. Obtain the transition table and show that the circuit is unstable when both T and CP are equal to 1.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

6
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
flipflop
0
votes
0
answers
16
Morris Mano Edition 3 Exercise 9 Question 6 (Page No. 393)
Investigate the transition table of the figure and determine all the race conditions whether they are critical or not critical. Also, determine whether there are any cycles.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

6
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
17
Morris Mano Edition 3 Exercise 9 Question 5 (Page No. 393)
Convert the flow table of the figure into a transition table by assigning the following binary values to the states: a = 00, b = 11, and c = 10. Assign values to the extra fourth state to avoid critical races. Assign output to the don’t care states to avoid momentary false output. Derive the logic diagram of the circuit.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

4
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
18
Morris Mano Edition 3 Exercise 9 Question 4 (Page No. 392)
An asynchronous sequential circuit has two internal states and one output. The excitation and output functions describing the circuit are as follows. $Y _1 = x _1x _2 + x _1y _2' + x _2'y _1$ ... Draw the logic diagram of the circuit. Derive the transition table and the output map. Obtain a flow table for the circuit.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

6
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
19
Morris Mano Edition 3 Exercise 9 Question 3 (Page No. 392)
an asynchronous circuit is described by the following excitation and output functions: $Y = x _1x _2’ + (x _1 + x _2’)y$ $z = y$ Draw the logic diagram of the circuit. Derive the transition table and the output map. obtain a twostate flow table. Describe in the words the behavior of the circuit.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

5
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
20
Morris Mano Edition 3 Exercise 9 Question 2 (Page No. 392)
Derive a transition table for the asynchronous sequential circuit given in the figure. Determine the sequence of the internal states $y _1Y _2$ for the following sequence of the input $x _1x _2$: 00,10,11,01,11,10,00.
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

5
views
digitallogic
digitalcircuits
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
21
Morris Mano Edition 3 Exercise 9 Question 1 (Page No. 392)
Explain the difference between synchronous and asynchronous sequential circuits. Define fundamental mode operation. Explain the difference between stable and unstable states. what is the difference between an internal state or a total state?
asked
Apr 7
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

5
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
descriptive
0
votes
0
answers
22
Morris Mano Edition 3 Exercise 7 Question 34 (Page No. 305)
Word number 535 in the memory shown in the figure contains the binary equivalent of 2209. List the 10 bit address and 16bit memory content of the word.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

2
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
23
Morris Mano Edition 3 Exercise 7 Question 33 (Page No. 305)
The following memory units are specified by the number of words times the number of bits per word. How many address lines and Input output data lines are needed in each case given below? $2K \times 16$; $64K \times 8$; $16M \times 32$; $96K \times 12$;
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

7
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
24
Morris Mano Edition 3 Exercise 7 Question 30 (Page No. 305)
Show the circuit and the timing diagram for generating six repeated timing signals, $T _0$ through $T _5$.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

3
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
digitalcircuits
0
votes
0
answers
25
Morris Mano Edition 3 Exercise 7 Question 29 (Page No. 305)
Add four 2input AND gates to the circuit of the figure. One input in each gate is connected to one output of the decoder. The other input in each gate is connected to the clock. Label the outputs of the AND gate as $P _0,P _1,P _2, and P _3$. Show the timing diagram of the for P outputs.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

6
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
26
Morris Mano Edition 3 Exercise 7 Question 28 (Page No. 305)
Using a start signal as in the figure , construct a word time control that stays on for a period of 16 clock pulses.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

3
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
0
votes
0
answers
27
Morris Mano Edition 3 Exercise 7 Question 23 (Page No. 304)
Design a synchronous BCD counter with JK flipflops
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

5
views
digitallogic
sequentialcircuit
digitalcounter
synchronousasynchronouscircuits
0
votes
0
answers
28
Morris Mano Edition 3 Exercise 7 Question 2,3 (Page No. 303)
Change the asynchronousclearcircuit of the figure to the synchronousclearcircuit, The modified register will have parallel load capability and asynchronous clear capability, but no asynchronous clear circuit. The register is cleared ... input CP goes through a negative transition while the D input of all the flipflops are 0.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

3
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
registers
0
votes
0
answers
29
Morris Mano Edition 3 Exercise 7 Question 1 (Page No. 303)
Include a 2input NAND gate with the register of the figure and connect the gate output to CP inputs of all the flipflops. One input of the NAND gate receives input from the clockpulsegenerator. Another input of NAND gate provides parallel load control. Explain the operation of the modified register.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

7
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
registers
0
votes
0
answers
30
Morris Mano Edition 3 Exercise 6 Question 25 (Page No. 255)
Design the following nonbinary sequence counter as specified in each case. Treat the unused states as don't cares conditions. Analyze the final circuit to ensure that it is selfcorrecting. If your design produces a nonselfcorrecting ... . Design a counter with the following repeated binary sequence 0,1,3, 7,6,4. Use T flipflops.
asked
Apr 6
in
Digital Logic
by
ajaysoni1924
Loyal
(
9.7k
points)

10
views
digitallogic
sequentialcircuit
synchronousasynchronouscircuits
digitalcounter
Page:
1
2
next »
Quick search syntax
tags
tag:apple
author
user:martin
title
title:apple
content
content:apple
exclude
tag:apple
force match
+apple
views
views:100
score
score:10
answers
answers:2
is accepted
isaccepted:true
is closed
isclosed:true
Recent Posts
IIT Madras Interview Experience
IIT Kanpur Interview Experience
IIIT Hderabad Interview Experience
IIT Delhi Interview Experience
IIT Hyderabad Interview Experience
Follow @csegate
Recent questions tagged synchronousasynchronouscircuits
Recent Blog Comments
10000 to <2000 is really kind of achievement , my...
THey removed it this year... I did not check it,...
even though i am not going for iiit , can you...
I don't think IIITD requires any codechef...
Will apply for IIITB. IIIT D requires a codechef...
50,132
questions
53,252
answers
184,790
comments
70,509
users