Recent questions tagged synchronous-asynchronous-circuits / GATE Overflow for GATE CSE

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31

Morris Mano Edition 3 Exercise 7 Question 34 (Page No. 305)
Word number 535 in the memory shown in the figure contains the binary equivalent of 2209. List the 10 bit address and 16-bit memory content of the word.

Word number 535 in the memory shown in the figure contains the binary equivalent of 2209. List the 10 bit address and 16-bit memory content of the word.

ajaysoni1924

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ajaysoni1924 asked Apr 6, 2019

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32

Morris Mano Edition 3 Exercise 7 Question 33 (Page No. 305)
The following memory units are specified by the number of words times the number of bits per word. How many address lines and Input output data lines are needed in each case given below? $2K \times 16$; $64K \times 8$; $16M \times 32$; $96K \times 12$;

The following memory units are specified by the number of words times the number of bits per word. How many address lines and Input output data lines are needed in each c...

ajaysoni1924

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ajaysoni1924 asked Apr 6, 2019

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33

Morris Mano Edition 3 Exercise 7 Question 30 (Page No. 305)
Show the circuit and the timing diagram for generating six repeated timing signals, $T _0$ through $T _5$.

Show the circuit and the timing diagram for generating six repeated timing signals, $T _0$ through $T _5$.

ajaysoni1924

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ajaysoni1924 asked Apr 6, 2019

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34

Morris Mano Edition 3 Exercise 7 Question 29 (Page No. 305)
Add four 2-input AND gates to the circuit of the figure. One input in each gate is connected to one output of the decoder. The other input in each gate is connected to the clock. Label the outputs of the AND gate as $P _0,P _1,P _2, and P _3$. Show the timing diagram of the for P outputs.

Add four 2-input AND gates to the circuit of the figure. One input in each gate is connected to one output of the decoder. The other input in each gate is connected to th...

ajaysoni1924

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ajaysoni1924 asked Apr 6, 2019

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35

Morris Mano Edition 3 Exercise 7 Question 28 (Page No. 305)
Using a start signal as in the figure , construct a word time control that stays on for a period of 16 clock pulses.

Using a start signal as in the figure , construct a word time control that stays on for a period of 16 clock pulses.

ajaysoni1924

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ajaysoni1924 asked Apr 6, 2019

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36

Morris Mano Edition 3 Exercise 7 Question 23 (Page No. 304)
Design a synchronous BCD counter with JK flip-flops

Design a synchronous BCD counter with JK flip-flops

ajaysoni1924

417 views

ajaysoni1924 asked Apr 6, 2019

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37

Morris Mano Edition 3 Exercise 7 Question 2,3 (Page No. 303)
Change the asynchronous-clear-circuit of the figure to the synchronous-clear-circuit, The modified register will have parallel load capability and asynchronous clear capability, but no asynchronous clear circuit. The register is cleared ... input CP goes through a negative transition while the D input of all the flip-flops are 0.

Change the asynchronous-clear-circuit of the figure to the synchronous-clear-circuit, The modified register will have parallel load capability and asynchronous clear capa...

ajaysoni1924

950 views

ajaysoni1924 asked Apr 6, 2019

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38

Morris Mano Edition 3 Exercise 7 Question 1 (Page No. 303)
Include a 2-input NAND gate with the register of the figure and connect the gate output to CP inputs of all the flip-flops. One input of the NAND gate receives input from the clock-pulse-generator. Another input of NAND gate provides parallel load control. Explain the operation of the modified register.

Include a 2-input NAND gate with the register of the figure and connect the gate output to CP inputs of all the flip-flops. One input of the NAND gate receives input from...

ajaysoni1924

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ajaysoni1924 asked Apr 6, 2019

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39

Morris Mano Edition 3 Exercise 6 Question 25 (Page No. 255)
Design the following non-binary sequence counter as specified in each case. Treat the unused states as don't cares conditions. Analyze the final circuit to ensure that it is self-correcting. If your design produces a non-self-correcting ... . Design a counter with the following repeated binary sequence 0,1,3, 7,6,4. Use T flip-flops.

Design the following non-binary sequence counter as specified in each case. Treat the unused states as don’t cares conditions. Analyze the final circuit to ensure that ...

ajaysoni1924

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ajaysoni1924 asked Apr 6, 2019

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1 answer

40

Morris Mano Edition 3 Exercise 6 Question 24 (Page No. 255)
Design the sequential circuit specified by the following state diagram using T flip-flop.

Design the sequential circuit specified by the following state diagram using T flip-flop.

ajaysoni1924

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ajaysoni1924 asked Apr 4, 2019

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41

Morris Mano Edition 3 Exercise 6 Question 23 (Page No. 255)
Design a sequential circuit specified by the following state transition diagram. using RS flip-flop.

Design a sequential circuit specified by the following state transition diagram. using RS flip-flop.

ajaysoni1924

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ajaysoni1924 asked Apr 4, 2019

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42

Morris Mano Edition 3 Exercise 6 Question 22 (Page No. 255)
A sequential circuit has three flip-flops, A, B, C; one input, x; one output, y; The state diagram is shown in the figure. The circuit is to be designed by treating the unused state as don't care conditions. The final circuit ... analyzed to ensure that it is self-correcting. Use D flip-flop in the design. USe JK flip-flops in the design .

A sequential circuit has three flip-flops, A, B, C; one input, x; one output, y; The state diagram is shown in the figure. The circuit is to be designed by treating the u...

ajaysoni1924

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ajaysoni1924 asked Apr 4, 2019

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43

Morris Mano Edition 3 Exercise 6 Question 21 (Page No. 255)
Design a sequential circuit with two JK flip-flops, A and B and two inputs, E and x. If E = 0 the circuit remains in the same state regardless of the value of x. When E = 1and x = 1, the circuit goes through the transactions from ... = 1 and x = 0 the circuit goes through the transactions from 00 to 11 to 10 to 01 back to 00, and repeats.

Design a sequential circuit with two JK flip-flops, A and B and two inputs, E and x. If E = 0 the circuit remains in the same state regardless of the value of x. When E =...

ajaysoni1924

354 views

ajaysoni1924 asked Apr 4, 2019

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44

Morris Mano Edition 3 Exercise 6 Question 20 (Page No. 255)
Design a sequential circuit with two D flip-flops A and B and one input, x. When x = 0 the state of the circuit remains the same. When x =1 circuit goes through the state transition from 00 to 01 to 1 to 10 back to 00 and, repeats.

Design a sequential circuit with two D flip-flops A and B and one input, x. When x = 0 the state of the circuit remains the same. When x =1 circuit goes through the state...

ajaysoni1924

311 views

ajaysoni1924 asked Apr 4, 2019

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45

Morris Mano Edition 3 Exercise 6 Question 19 (Page No. 254)
Convert a D flip-flop to JK flip-flop by including input gates to the D flip-flop. The gates need for the input of the D flip-flop can be determined by means of the sequential circuit design procedure. The sequential circuit to be considered will have one D flip-flop and two inputs, J and K.

Convert a D flip-flop to JK flip-flop by including input gates to the D flip-flop. The gates need for the input of the D flip-flop can be determined by means of the seque...

ajaysoni1924

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ajaysoni1924 asked Apr 4, 2019

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46

Morris Mano Edition 3 Exercise 6 Question 18 (Page No. 254)
Analyze the circuit in the following figure and show that it is equivalent to T flip-flop.

Analyze the circuit in the following figure and show that it is equivalent to T flip-flop.

ajaysoni1924

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ajaysoni1924 asked Apr 4, 2019

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1 answer

47

Morris Mano Edition 3 Exercise 6 Question 15,16 (Page No. 254)
Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011. reduce the same table and repeat the same sequence with the given input sequence. Show that same output is obtained.

Starting from a state of the state table given below find out the output sequence generated with an input sequence 01110010011.reduce the same table and repeat the same ...

ajaysoni1924

2.1k views

ajaysoni1924 asked Apr 4, 2019

2 votes

1 answer

48

Morris Mano Edition 3 Exercise 6 Question 14 (Page No. 254)
Reduce the number of states in the following state table and tabulate the reduced state table.

Reduce the number of states in the following state table and tabulate the reduced state table.

ajaysoni1924

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ajaysoni1924 asked Apr 4, 2019

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49

Morris Mano Edition 3 Exercise 6 Question 13 (Page No. 254)
Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence of 010110111011110 is applied.

Starting from state 00 in the state transition diagram of the figure. Determine the state transitions and output sequence that will be generated when the input sequence o...

ajaysoni1924

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ajaysoni1924 asked Apr 4, 2019

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2 answers

50

Synchronous Counter Circuit
In the given synchronous Counter circuit, initially all Outputs are Reset. It is required to replace FF2 with AB Flip Flop. The FF2 inputs would be:- A. A = Q1 and B = Q1' B. A = Q1' and B = Q1' C. A = Q1.Q0 and B = Q1.Q0 D. A = Qo' and B = Qo'

In the given synchronous Counter circuit, initially all Outputs are Reset. It is required to replace FF2 with AB Flip Flop. The FF2 inputs would be:- A. A = Q1 and B = Q1...

Na462

479 views

Na462 asked Oct 10, 2018

1 votes

1 answer

51

Synchronous Counter

Na462

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Na462 asked Oct 1, 2018

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1 answer

52

MadeEasy Test Series: Digital Logic - Synchronous Counter
Consider the following synchronous counter made up of JK,D,T flip flops as in the image! now here why J is taken as Q0' (complement) instead of Q0'' (double complement) you can clearly see a bubble and a q0' ... as it should be so q0'' right? please clarify!

Consider the following synchronous counter made up of JK,D,T flip flops as in the image!now here why J is taken as Q0' (complement) instead of Q0'' (double complement) y...

vishnu priyan

1.1k views

vishnu priyan asked Dec 14, 2017

1 votes

1 answer

53

Virtual Gate Test Series: Digital Logic - Counter

Manoja Rajalakshmi A

363 views

Manoja Rajalakshmi A asked Nov 12, 2017

2 votes

1 answer

54

MadeEasy Subject Test: Digital Logic - Flip Flop
For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the maximum frequency of MOD 256 counter ?(in MHz) a)18.18 b)19.18 c)20. ... makes Frequency = 1/(30 nsec) = 33.33 Mhz? please correct me where I am going wrong. Thanks for your help :)

For synchronous series counter of modulus 256, the propagation delay for each flip flop is 25 nsec and propagation delay of each two input AND gate is 5 nsec. What is the...

Kamal Pratap

502 views

Kamal Pratap asked Oct 10, 2017

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55

doubt -synchronous counter
what is the correct way to design synchronous counter ?for any arbitrary sequence like 7,3,1,2,5,4,6,7,3,1,2,4,5,6 I simply using state table diagram and by minimization it is easy to design circuit.Also to identify minimum number ... flop in synchronous counter I just calculating number of bits used in counter . pls tell correct approach to solve these type of problems

what is the correct way to design synchronous counter ?for any arbitrary sequence like 7,3,1,2,5,4,6,7,3,1,2,4,5,6 I simply using state table diagram and by minimizatio...

set2018

304 views

set2018 asked Oct 2, 2017

1 votes

2 answers

56

gate 2014
which is faster, synchronous circuits or asynchronous circuits and why?

which is faster, synchronous circuits or asynchronous circuits and why?

Sunil8860

1.4k views

Sunil8860 asked Aug 29, 2017

3 votes

1 answer

57

Test by Bikram | Mock GATE | Test 4 | Question: 51
In a synchronous series counter of Modulus $256$, the propagation delay for each $2$ input AND gate is $5$ ns and for each flip-flop is $25$ ns. The maximum frequency of the Mod-256 counter is _____MHz.

In a synchronous series counter of Modulus $256$, the propagation delay for each $2$ input AND gate is $5$ ns and for each flip-flop is $25$ ns. The maximum frequency of ...

Bikram

910 views

Bikram asked May 14, 2017

1 votes

3 answers

58

Virtual Gate Test Series: Digital Logic - Asynchronous Counter

Hradesh patel

960 views

Hradesh patel asked Oct 8, 2016

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2 answers

59

MadeEasy Workbook: Digital Logic - Synchronous Asynchronous Circuits

Payal Rastogi

866 views

Payal Rastogi asked Dec 25, 2015

23 votes

3 answers

60

GATE CSE 1998 | Question: 16
Design a synchronous counter to go through the following states:$1, 4, 2, 3, 1, 4, 2, 3, 1, 4 \dots $

Design a synchronous counter to go through the following states:$$1, 4, 2, 3, 1, 4, 2, 3, 1, 4 \dots $$

Kathleen

5.1k views

Kathleen asked Sep 26, 2014

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