Recent questions tagged tanenbaum / GATE Overflow for GATE CSE

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181

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 26 (Page No. 256)
A student in a compiler design course proposes to the professor a project of writing a compiler that will produce a list of page references that can be used to implement the optimal page replacement algorithm. Is this possible? Why or why not? Is there anything that could be done to improve paging efficiency at run time?

A student in a compiler design course proposes to the professor a project of writing a compiler that will produce a list of page references that can be used to implement ...

admin

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admin asked Oct 26, 2019

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182

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 25 (Page No. 256)
A computer with an $8-KB$ page, a $256-KB$ main memory, and a $64-GB$ virtual address space uses an inverted page table to implement its virtual memory. How big should the hash table be to ensure a mean hash chain length of less than $1?$ Assume that the hash table size is a power of two.

A computer with an $8-KB$ page, a $256-KB$ main memory, and a $64-GB$ virtual address space uses an inverted page table to implement its virtual memory. How big should th...

admin

499 views

admin asked Oct 26, 2019

1 votes

4 answers

183

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 24 (Page No. 256)
A machine has $48-bit$ virtual addresses and $32-bit$ physical addresses. Pages are $8\: KB.$ How many entries are needed for a single-level linear page table?

A machine has $48-bit$ virtual addresses and $32-bit$ physical addresses. Pages are $8\: KB.$ How many entries are needed for a single-level linear page table?

admin

720 views

admin asked Oct 26, 2019

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184

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 23 (Page No. 256)
How can the associative memory device needed for a $TLB$ be implemented in hardware, and what are the implications of such a design for expandability?

How can the associative memory device needed for a $TLB$ be implemented in hardware, and what are the implications of such a design for expandability?

admin

282 views

admin asked Oct 26, 2019

1 votes

1 answer

185

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 22 (Page No. 256)
A computer whose processes have $1024$ pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is $5\: nsec.$ To reduce this overhead, the computer has a $TLB,$ ... a lookup in $1\: nsec.$ What hit rate is needed to reduce the mean overhead to $2\: nsec?$

A computer whose processes have $1024$ pages in their address spaces keeps its page tables in memory. The overhead required for reading a word from the page table is $5\:...

admin

790 views

admin asked Oct 26, 2019

1 votes

0 answers

186

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 21 (Page No. 256)
Below is an execution trace of a program fragment for a computer with $512-byte$ pages. The program is located at address $1020,$ and its stack pointer is at $8192\:\:($the stack grows toward $0).$ Give the ... $16$ from the stack pointer Compare the actual parameter to the immediate constant $4$ Jump if equal to $5152$

Below is an execution trace of a program fragment for a computer with $512-byte$ pages. The program is located at address $1020,$ and its stack pointer is at $8192\:\:($t...

admin

455 views

admin asked Oct 26, 2019

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187

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 20 (Page No. 256)
A computer has $32-bit$ virtual addresses and $4-KB$ pages. The program and data together fit in the lowest page $(0-4095)$ The stack fits in the highest page. How many entries are needed in the page table if ... paging is used? How many page table entries are needed for two-level paging, with $10$ bits in each part?

A computer has $32-bit$ virtual addresses and $4-KB$ pages. The program and data together fit in the lowest page $(0–4095)$ The stack fits in the highest page. How many...

admin

571 views

admin asked Oct 26, 2019

4 votes

4 answers

188

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 19 (Page No. 256)
A computer with a $32-bit$ address uses a two-level page table. Virtual addresses are split into a $9-bit$ top-level page table field, an $11-bit$ second-level page table field, and an offset. How large are the pages and how many are there in the address space?

A computer with a $32-bit$ address uses a two-level page table. Virtual addresses are split into a $9-bit$ top-level page table field, an $11-bit$ second-level page table...

admin

2.7k views

admin asked Oct 26, 2019

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189

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 18 (Page No. 256)
Section $3.3.4$ states that the Pentium Pro extended each entry in the page table hierarchy to $64$ bits but still could only address only $4\: GB$ of memory. Explain how this statement can be true when page table entries have $64$ bits.

Section $3.3.4$ states that the Pentium Pro extended each entry in the page table hierarchy to $64$ bits but still could only address only $4\: GB$ of memory. Explain how...

admin

323 views

admin asked Oct 26, 2019

1 votes

1 answer

190

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 17 (Page No. 255)
Suppose that a machine has $438-bit$ virtual addresses and $32-bit$ physical addresses. What is the main advantage of a multilevel page table over a single-level one? With a two-level page table, $16-KB$ pages, ... should be allocated for the top-level page table field and how many for the next level page table field? Explain.

Suppose that a machine has $438-bit$ virtual addresses and $32-bit$ physical addresses.What is the main advantage of a multilevel page table over a single-level one?With ...

admin

2.4k views

admin asked Oct 26, 2019

1 votes

2 answers

191

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 16 (Page No. 255)
You are given the following data about a virtual memory system: The $TLB$ can hold $1024$ entries and can be accessed in $1$ clock cycle $(1\: nsec).$ A page table entry can be found in $100$ ... $0.01\%$ lead to a page fault, what is the effective address-translation time?

You are given the following data about a virtual memory system:The $TLB$ can hold $1024$ entries and can be accessed in $1$ clock cycle $(1\: nsec).$ A page table entry c...

admin

671 views

admin asked Oct 26, 2019

2 votes

1 answer

192

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 15 (Page No. 255)
Suppose that a machine has $48-bit$ virtual addresses and $32-bit$ physical addresses. If pages are $4\: KB$, how many entries are in the page table if it has only a single level? Explain. Suppose this same ... long integer elements from an array that spans thousands of pages. How effective will the $TLB$ be for this case?

Suppose that a machine has $48-bit$ virtual addresses and $32-bit$ physical addresses.If pages are $4\: KB$, how many entries are in the page table if it has only a singl...

admin

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admin asked Oct 26, 2019

2 votes

1 answer

193

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 14 (Page No. 255)
A machine has a $32-bit$ address space and an $8-KB$ page. The page table is entirely in hardware, with one $32-bit$ word per entry. When a process starts, the page table is copied to the hardware from memory, ... including the time to load the page table), what fraction of the $CPU$ time is devoted to loading the page tables?

A machine has a $32-bit$ address space and an $8-KB$ page. The page table is entirely in hardware, with one $32-bit$ word per entry. When a process starts, the page table...

admin

390 views

admin asked Oct 26, 2019

1 votes

2 answers

194

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 13 (Page No. 255)
If an instruction takes $1\: nsec$ and a page fault takes an additional $n\: nsec,$ give a formula for the effective instruction time if page faults occur every $k$ instructions.

If an instruction takes $1\: nsec$ and a page fault takes an additional $n\: nsec,$ give a formula for the effective instruction time if page faults occur every $k$ instr...

admin

1.7k views

admin asked Oct 26, 2019

0 votes

2 answers

195

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 12 (Page No. 255)
The amount of disk space that must be available for page storage is related to the maximum number of processes$,\: n,$ the number of bytes in the virtual address space, $v,$ and the number of bytes of $RAM,\: r$. Give an expression for the worst-case disk-space requirements. How realistic is this amount?

The amount of disk space that must be available for page storage is related to the maximum number of processes$,\: n,$ the number of bytes in the virtual address space, $...

admin

1.1k views

admin asked Oct 26, 2019

1 votes

1 answer

196

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 11 (Page No. 255)
Consider the following C program: int X[N]; int step = M; /* M is some predefined constant */ for (int i = 0; i < N; i += step) X[i] = X[i] + 1; If this program is run on a machine with ... for every execution of the inner loop? Would your answer in part $(a)$ be different if the loop were repeated many times? Explain.

Consider the following C program: int X[N]; int step = M; /* M is some predefined constant */ for (int i = 0; i < N; i += step) X[i] = X[i] + 1;If this program is run on ...

admin

597 views

admin asked Oct 26, 2019

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197

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 10 (Page No. 255)
Copy on write is an interesting idea used on server systems. Does it make any sense on a smartphone?

Copy on write is an interesting idea used on server systems. Does it make any sense on a smartphone?

admin

150 views

admin asked Oct 26, 2019

0 votes

1 answer

198

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 9 (Page No. 255)
What kind of hardware support is needed for a paged virtual memory to work?

What kind of hardware support is needed for a paged virtual memory to work?

admin

368 views

admin asked Oct 26, 2019

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0 answers

199

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 8 (Page No. 254)
The Intel $8086$ processor did not have an MMU or support virtual memory. Nevertheless, some companies sold systems that contained an unmodified $8086$ CPU and did paging. Make an educated guess as to how they did it. (Hint: Think about the logical location of the MMU.)

The Intel $8086$ processor did not have an MMU or support virtual memory. Nevertheless, some companies sold systems that contained an unmodified $8086$ CPU and did paging...

admin

336 views

admin asked Oct 26, 2019

1 votes

0 answers

200

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 7 (Page No. 254)
Using the page table of Fig. $3-9,$ give the physical address corresponding to each of the following virtual addresses: $20$ $4100$ $8300$

Using the page table of Fig. $3-9,$ give the physical address corresponding to each of the following virtual addresses:$20$$4100$$8300$

admin

596 views

admin asked Oct 26, 2019

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0 answers

201

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 6 (Page No. 254)
For each of the following decimal virtual addresses, compute the virtual page number and offset for a $4-KB$ page and for an $8 KB$ page$:20000, 32768, 60000.$

For each of the following decimal virtual addresses, compute the virtual page number and offset for a $4-KB$ page and for an $8 KB$ page$:20000, 32768, 60000.$

admin

349 views

admin asked Oct 26, 2019

1 votes

1 answer

202

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 5 (Page No. 254)
What is the difference between a physical address and a virtual address?

What is the difference between a physical address and a virtual address?

admin

474 views

admin asked Oct 25, 2019

1 votes

2 answers

203

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 4 (Page No. 254)
Consider a swapping system in which memory consists of the following hole sizes in memory order: $10\: MB, 4\: MB, 20\: MB, 18\: MB, 7\: MB, 9\: MB, 12\: MB,$ and $15\: MB$. Which hole is taken for successive segment ... $10\: MB$ $9\: MB$ for first fit? Now repeat the question for best fit, worst fit, and next fit.

Consider a swapping system in which memory consists of the following hole sizes in memory order: $10\: MB, 4\: MB, 20\: MB, 18\: MB, 7\: MB, 9\: MB, 12\: MB,$ and $15\: M...

admin

6.1k views

admin asked Oct 25, 2019

0 votes

2 answers

204

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 3 (Page No. 254)
A swapping system eliminates holes by compaction. Assuming a random distribution of many holes and many data segments and a time to read or write a $32-bit$ memory word of $4\:nsec$, about how long does it take to ... simplicity, assume that word $0$ is part of a hole and that the highest word in memory contains valid data.

A swapping system eliminates holes by compaction. Assuming a random distribution of many holes and many data segments and a time to read or write a $32-bit$ memory word o...

admin

1.3k views

admin asked Oct 25, 2019

0 votes

1 answer

205

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 2 (Page No. 254)
In Fig. $3-3$ the base and limit registers contain the same value, $16,384$. Is this just an accident, or are they always the same? It is just an accident, why are they the same in this example?

In Fig. $3-3$ the base and limit registers contain the same value, $16,384$. Is this just an accident, or are they always the same? It is just an accident, why are they t...

admin

1.5k views

admin asked Oct 25, 2019

0 votes

1 answer

206

Andrew S. Tanenbaum (OS) Edition 4 Exercise 3 Question 1 (Page No. 254)
The $IBM\:360$ had a scheme of locking $2-KB$ blocks by assigning each one a $4-bit$ key and having the CPU compare the key on every memory reference to the $4-bit$ key in the $PSW$. Name two drawbacks of this scheme not mentioned in the text.

The $IBM\:360$ had a scheme of locking $2-KB$ blocks by assigning each one a $4-bit$ key and having the CPU compare the key on every memory reference to the $4-bit$ key i...

admin

381 views

admin asked Oct 25, 2019

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0 answers

207

Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 65 (Page No. 180)
Implement a program to count the frequency of words in a text file. The text file is partitioned into $N$ segments. Each segment is processed by a separate thread that outputs the intermediate frequency ... the threads complete; then it computes the consolidated word-frequency data based on the individual threads' output.

Implement a program to count the frequency of words in a text file. The text file is partitioned into $N$ segments. Each segment is processed by a separate thread that ou...

admin

363 views

admin asked Oct 25, 2019

1 votes

0 answers

208

Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 64 (Page No. 179 - 180)
The objective of this exercise is to implement a multithreaded solution to find if a given number is a perfect number. $N$ is a perfect number if the sum of all its factors, excluding itself, is $N;$ examples are ... can make the computation faster by restricting the numbers searched from $1$ to the square root of $N.)$

The objective of this exercise is to implement a multithreaded solution to find if a given number is a perfect number. $N$ is a perfect number if the sum of all its facto...

admin

365 views

admin asked Oct 25, 2019

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209

Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 63 (Page No. 179)
A process can be put into a round-robin queue more than once to give it a higher priority. Running multiple instances of a program each working on a different part of a data pool can have the same effect. First write a ... but on a system with other processes, you should be able to grab a bigger share of the CPU this way.

A process can be put into a round-robin queue more than once to give it a higher priority. Running multiple instances of a program each working on a different part of a d...

admin

328 views

admin asked Oct 25, 2019

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0 answers

210

Andrew S. Tanenbaum (OS) Edition 4 Exercise 2 Question 62 (Page No. 179)
Write a producer-consumer problem that uses threads and shares a common buffer. However, do not use semaphores or any other synchronization primitives to guard the shared data structures. Just let each thread access them when ... Do not print more than one number every minute because the I/O could affect the race conditions.

Write a producer-consumer problem that uses threads and shares a common buffer. However, do not use semaphores or any other synchronization primitives to guard the shared...

admin

716 views

admin asked Oct 25, 2019

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