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Recent questions tagged tbb-coa-1
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Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 30
Consider the following program segment for a CPU having three Registers $R1, R2,$ and $R3$ ... the Multiply' instruction is being executing by the CPU, then the return address saved onto the stack will be _______.
Consider the following program segment for a CPU having three Registers $R1, R2,$ and $R3$:$$ \begin{array}{|l|l|l|} \hline \text{Instruction} & \text{Operation} & \text{...
Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
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1
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1
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2
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 29
A CPU has a $32$ KB direct-mapped cache with $128$byte block size. $'A'$ is a two dimensional array of size $512 \times 512$ with elements that occupy $8$bytes each. for (j=0; j<512; j++) { for (i=0; i<512; i++) { x + ... i]; } } The number of cache misses in row major order is: $2^{11}$ $2^{14}$ $2^{18}$ $2^{15}$
A CPU has a $32$ KB direct-mapped cache with $128$byte block size. $’A’$ is a two dimensional array of size $512 \times 512$ with elements that occupy $8$bytes each.f...
Bikram
392
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
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1
votes
1
answer
3
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 28
A computer system has a main memory consisting of $1$M $16$-bit words. It also has a $4$K-word cache organized in the block-set-associative manner (with $4$ blocks per set and $64$ words per block). Assume that the cache ... . [Assume that the LRU algorithm is used for block replacement.] $3.19$ $3.16$ $2.15$ $2.19$
A computer system has a main memory consisting of $1$M $16$-bit words. It also has a $4$K-word cache organized in the block-set-associative manner (with $4$ blocks per se...
Bikram
439
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
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–
0
votes
1
answer
4
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 27
The memory unit of a computer has $256$ K words of $32$ bits each. The computer has an instruction format with four fields: an operation code field, a mode field (to specify one of seven addressing modes), a register address field (to ... Register address Memory address $6,5,3,18$ $5,6,3,18$ $5,18,6,3$ $5,3,6,18$
The memory unit of a computer has $256$ K words of $32$ bits each. The computer has an instruction format with four fields: an operation code field, a mode field (to spec...
Bikram
252
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
instruction-format
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0
votes
1
answer
5
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 26
A block-set-associative cache consists of a total of $64$ blocks divided into $4$-block sets. The main memory contains $4096$ blocks (each consisting of $128$ words). Answer the following questions based on this info: How many bits are there in a main ... and $8,7,4$ $20$ and $6,7,8$ $19$ and $8,4,7$ $17$ and $8,7,4$
A block-set-associative cache consists of a total of $64$ blocks divided into $4$-block sets. The main memory contains $4096$ blocks (each consisting of $128$ words).Answ...
Bikram
339
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
cache-memory
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0
votes
1
answer
6
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 25
What is the addressing mode of the below mentioned instruction? $’\text{MUL } \ R1, \ \#2’$ Indirect Indexed Immediate Direct
What is the addressing mode of the below mentioned instruction?$’\text{MUL } \ R1, \ \#2’$ Indirect Indexed Immediate Direct
Bikram
224
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
addressing-modes
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–
1
votes
1
answer
7
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 24
Consider two pipelines A and B. Pipeline A has $8$ stages with uniform stage delay of $2$ns. Pipeline B has $5$ stages with uniform stage delays of $3$ns. Time saved (in ns) by pipeline A compared to pipeline B to execute $100$ instructions is _____.
Consider two pipelines A and B. Pipeline A has $8$ stages with uniform stage delay of $2$ns. Pipeline B has $5$ stages with uniform stage delays of $3$ns. Time saved (in ...
Bikram
270
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
pipelining
speedup
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–
3
votes
2
answers
8
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 23
A hard disk is connected to a $2$ GHz processor through a DMA controller which works in burst mode. The initial set up of a DMA transfer takes $1000$ ... is $16$ KB. Then, the fraction of CPU time free if the disk is transferring data is _______%.
A hard disk is connected to a $2$ GHz processor through a DMA controller which works in burst mode. The initial set up of a DMA transfer takes $1000$ clock cycles for the...
Bikram
1.0k
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
io-handling
dma
+
–
1
votes
3
answers
9
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 22
Consider a hypothetical processor that supports two addresses -- one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is placed in $1$ word of ... instructions and $1984$ one address instructions, then the total number of zero address instructions formulated are _______.
Consider a hypothetical processor that supports two addresses one address and zero address instructions. It has a $256$ word memory, and a $20$ bit instruction is place...
Bikram
414
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
instruction-format
numerical-answers
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2
votes
2
answers
10
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 21
In a computer system, there are $5$ registers, namely -- $PC, AR, DR, IR,$ and $SC$. The initial content of $PC$ is $7FF$. The content of memory at address $7FF$ is $EA9F$; at address $A9F$ is ... and executed, the content of $PC$ register after $6$ clock pulse is ________ (put the integer value of register content).
In a computer system, there are $5$ registers, namely $PC, AR, DR, IR,$ and $SC$. The initial content of $PC$ is $7FF$. The content of memory at address $7FF$ is $EA9F$...
Bikram
1.7k
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
machine-instruction
numerical-answers
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–
2
votes
3
answers
11
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 20
A computer has $32$ bit instructions and $12$ bit addresses. If there are $250$ two-address instructions, the number of one-address instructions that can be formulated are ______.
A computer has $32$ bit instructions and $12$ bit addresses.If there are $250$ two-address instructions, the number of one-address instructions that can be formulated are...
Bikram
597
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Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
instruction-format
+
–
0
votes
1
answer
12
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 19
In an $8$ segment pipeline, the total number of clock pulses that process $150$ tasks are ______ cycles.
In an $8$ segment pipeline, the total number of clock pulses that process $150$ tasks are ______ cycles.
Bikram
217
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
clock-cycles
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–
0
votes
2
answers
13
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 18
In a system, cache memory access time is $100ns$ and the main memory is $10$ times slower than cache memory. The hit ratio for read request is $0.92$ ... . The average access time (in ns) considering both read & write requests (using write-through policy) is ______.
In a system, cache memory access time is $100ns$ and the main memory is $10$ times slower than cache memory. The hit ratio for read request is $0.92$.Of the memory reques...
Bikram
579
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
cache-memory
numerical-answers
+
–
0
votes
2
answers
14
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 17
The fastest mode of data transfer is: Programmable I/O Interrupt I/O DMA Both A and B
The fastest mode of data transfer is:Programmable I/OInterrupt I/ODMABoth A and B
Bikram
445
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
io-handling
interrupts
dma
+
–
3
votes
1
answer
15
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 16
A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots $85$ % of the time, and can fill the second slot only $20$ % of the time. ... the instructions executed are branch instructions, then the percentage improvement in performance achieved by this optimization is ________%.
A pipelined processor has two branch delay slots. An optimizing compiler can fill one of these slots $85$ % of the time, and can fill the second slot only $20$ % of the t...
Bikram
1.3k
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
pipelining
speedup
numerical-answers
+
–
3
votes
2
answers
16
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 15
An instruction is stored at location $300$ with its address field at location $301$. The address field has a value of $400$. A processor register $R1$ contains the number $200$. If relative-addressing mode is used by the instruction (with $R1$ as index register) then the effective address is _________.
An instruction is stored at location $300$ with its address field at location $301$. The address field has a value of $400$. A processor register $R1$ contains the number...
Bikram
1.1k
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
addressing-modes
+
–
0
votes
1
answer
17
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 14
A disk has $20$ sectors per track. Assume there are $512$ bytes per sector. What is the data transfer rate (in bytes per second) at a rotational speed of $7200$ rpm? $1.26 * 10^8$ bytes/second $1.58 * 10^6$ bytes/second $1.318 * 10^5$ bytes/second $1.2288 * 10^6$ bytes/second
A disk has $20$ sectors per track. Assume there are $512$ bytes per sector. What is the data transfer rate (in bytes per second) at a rotational speed of $7200$ rpm?$1.26...
Bikram
359
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
operating-system
disk
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–
0
votes
2
answers
18
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 13
A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns. The speed-up rotation of the pipeline for $10$ tasks will be _______.
A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns.The speed-up rotation of the p...
Bikram
315
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
pipelining
speedup
numerical-answers
+
–
0
votes
1
answer
19
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 12
A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four $16$-bit words (the data field), and each word has an associated $13$-bit tag field. When a miss occurs during a read ... number of Main memory access at the end of the First pass through the loop? $3$ $4$ $6$ $8$
A computer uses a small direct-mapped cache between the main memory and the processor. The cache has four $16$-bit words (the data field), and each word has an associated...
Bikram
467
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
machine-instruction
+
–
1
votes
2
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20
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 10
Registers $R1$ and $R2$ of a computer contain the decimal values $1300$ and $4500$. The following instructions are run: $\text{ Load 20(R1),R5}$ $\text{Move #3000,R5}$ $\text{Store R5,30(R1,R2)}$ The effective address of the memory operand is ___________.
Registers $R1$ and $R2$ of a computer contain the decimal values $1300$ and $4500$. The following instructions are run:$\text{ Load 20(R1),R5}$$\text{Move #3000,R5}$$\tex...
Bikram
678
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
machine-instruction
numerical-answers
+
–
2
votes
3
answers
21
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 11
A system has $3$ levels of cache i.e., $L_1, L_2$ and $L_3.$ The access times of $L_1,L_2$ and $L_3$ cache memories are $100$ ns/word, $150$ ns/word and $250$ ns/word, respectively. $L_1, L_2$ ... until a complete memory block gets transferred, what is the average access time? $103$ ns $220$ ns $150$ ns $135$ ns
A system has $3$ levels of cache i.e., $L_1, L_2$ and $L_3.$ The access times of $L_1,L_2$ and $L_3$ cache memories are $100$ ns/word, $150$ ns/word and $250$ ns/word, re...
Bikram
979
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
cache-memory
multilevel-cache
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–
2
votes
3
answers
22
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 9
A byte-addressable computer has a small data cache capable of holding eight $32$-bit words. Each cache block consists of one $32$-bit word. When a given program is executed, the processor reads data from the following ... cache is initially empty. If a direct-mapped cache is used, then the hit rate is __________ $\%$
A byte-addressable computer has a small data cache capable of holding eight $32$-bit words. Each cache block consists of one $32$-bit word. When a given program is execut...
Bikram
806
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
+
–
0
votes
1
answer
23
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 8
A link between the CPU and the user is provided by: Peripheral Devices Storage Control Unit Software
A link between the CPU and the user is provided by:Peripheral DevicesStorageControl UnitSoftware
Bikram
322
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Bikram
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Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
+
–
1
votes
4
answers
24
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 5
Which of the following is displacement addressing mode? Relative Indexed Base Immediate
Which of the following is displacement addressing mode?RelativeIndexedBaseImmediate
Bikram
958
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Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
addressing-modes
easy
+
–
0
votes
1
answer
25
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 7
A disk unit has $24$ recording surfaces and a total of $14,000$ cylinders. There is an average of $400$ sectors per track. Each sector contains $512$ bytes of data. What are the maximum number of bytes that can be stored in this unit? $67.80 * 10^9$ B $68.90 * 10^7$ B $68.80 * 10^9$ B $69.87 * 10^9$ B
A disk unit has $24$ recording surfaces and a total of $14,000$ cylinders. There is an average of $400$ sectors per track. Each sector contains $512$ bytes of data.What a...
Bikram
538
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Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
+
–
1
votes
1
answer
26
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 6
An interrupt that can temporarily be ignored by the computer is called: Vectored Interrupt Non-Maskable Interrupt Scalar Interrupt Maskable Interrupt
An interrupt that can temporarily be ignored by the computer is called: Vectored Interrupt Non-Maskable Interrupt Scalar Interrupt Maskable Interrupt
Bikram
288
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Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
+
–
0
votes
1
answer
27
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 4
A direct-mapped cache has $2^{10}$ cache lines with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a byte addressable memory of size $2^{30}$ bytes, then how many bytes of space will be required for storing the tags? $2^{15}$ bytes $2^{11}$ bytes $2^6$ KB $2^7$ KB
A direct-mapped cache has $2^{10}$ cache lines with $2^4$ bytes of data per cache line. If the cache is used to store blocks for a byte addressable memory of size $2^{...
Bikram
439
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
cache-memory
+
–
1
votes
1
answer
28
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 3
A hard disk system has the following parameters: Rotation speed - $6000$ rpm. Size of each sector - $1$ KB. Average number of sectors per track - $128$. Based on these parameters, which of the following statements is/are CORRECT? The ... per track is larger than $1$ MB. I only I and III only I and II only I, II, and III
A hard disk system has the following parameters:Rotation speed – $6000$ rpm.Size of each sector – $1$ KB.Average number of sectors per track – $128$.Based on these ...
Bikram
432
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Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
+
–
1
votes
1
answer
29
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 2
In a seven-segment pipeline, each segment takes $1$ cycle. Assuming there are no stalls, the number of clock cycles required to process $180$ tasks in a seven – segment pipeline is _______ cycles.
In a seven-segment pipeline, each segment takes $1$ cycle. Assuming there are no stalls, the number of clock cycles required to process $180$ tasks in a seven – segment...
Bikram
346
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
numerical-answers
pipelining
clock-cycles
+
–
1
votes
1
answer
30
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 1
We have two implementations of the same Instruction Set Architecture (ISA). Machine $A$ has a clock cycle time of $50$ ns and a CPI of $4.0$ for a program, while machine $B$ has a clock cycle of $65$ ns and a ... is TRUE? Machine A is faster than B. Machine B is faster than A. Both have the same speed. None of the above
We have two implementations of the same Instruction Set Architecture (ISA). Machine $A$ has a clock cycle time of $50$ ns and a CPI of $4.0$ for a program, while machine ...
Bikram
337
views
Bikram
asked
Nov 25, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
speedup
+
–
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