Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Recent questions tagged translation-lookaside-buffer
2
votes
0
answers
61
tanenbaum OS
Compute the run time of a program which has 55.500.000 memory accesses, a TLB hit rate of 75%, and a page fault rate of 0,005. We consider the TLB access time negligible. The page fault rate is the percent of memory accesses that require a disk access. ... TLB miss, the OS accesses the memory to get the page table entry and updates the TLB. Which is the run time of the application??
Compute the run time of a program which has 55.500.000 memory accesses, a TLB hit rate of 75%, and a page fault rate of 0,005. We consider the TLB access time negligible....
sushmita
439
views
sushmita
asked
Oct 1, 2016
Operating System
operating-system
translation-lookaside-buffer
paging
tanenbaum
+
–
4
votes
1
answer
62
made easy test
A computer system with 2 level paging scheme in which regular memory access takes 300 nanoseconds and servicing a pagefault takes 500ns. An average instruction takes 200 ns of CPU time and one memory access. The TLB hit ratio is 80% and page fault ratio is 20%. The average instruction execution time is ? My answer is 660 ns but made easy solution has 580 ns. Can any one check??
A computer system with 2 level paging scheme in which regular memory access takes 300 nanoseconds and servicing a pagefault takes 500ns. An average instruction takes 200 ...
sushmita
1.7k
views
sushmita
asked
Sep 29, 2016
Operating System
paging
operating-system
translation-lookaside-buffer
+
–
0
votes
1
answer
63
standrard co question with a bit of confusion
Considering hierarchical method,is my this equation correct? Assuming tlb access time as 0 ns EMAT = 300 [memory access time] + 0.2*(300*2)[2 level page table] + 0.2 * (500) Average instruction execution time = Emat + 200. = 720 ns.
Considering hierarchical method,is my this equation correct?Assuming tlb access time as 0 nsEMAT = 300 [memory access time] + 0.2*(300*2)[2 level page table] + 0.2 * (500...
resilientknight
393
views
resilientknight
asked
Sep 3, 2016
CO and Architecture
translation-lookaside-buffer
effective-memory-access
page-fault
+
–
0
votes
1
answer
64
easy and tricky co question
resilientknight
387
views
resilientknight
asked
Sep 3, 2016
CO and Architecture
translation-lookaside-buffer
co-and-architecture
paging
+
–
1
votes
1
answer
65
UGC NET CSE | December 2013 | Part 2 | Question: 47
The virtual address generated by a CPU is 32 bits. The Translation Look-aside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4-cache lines in the set). The page size is 4 KB. The minimum size of TLB tag is 12 bits 15 bits 16 bits 20 bits
The virtual address generated by a CPU is 32 bits. The Translation Look-aside Buffer (TLB) can hold total 64 page table entries and a 4-way set associative (i.e. with 4-c...
go_editor
4.7k
views
go_editor
asked
Jul 26, 2016
Operating System
ugcnetcse-dec2013-paper2
operating-system
translation-lookaside-buffer
+
–
7
votes
3
answers
66
ISRO2014-26
The output of a tristate buffer when the enable input in $0$ is Always $0$ Always $1$ Retains the last value when enable input was high Disconnected state
The output of a tristate buffer when the enable input in $0$ isAlways $0$Always $1$Retains the last value when enable input was highDisconnected state
go_editor
3.8k
views
go_editor
asked
Jul 1, 2016
Digital Logic
isro2014
digital-logic
translation-lookaside-buffer
+
–
4
votes
2
answers
67
TLB ,VGATE
@Arjun sir, I solved it by using the same concept of gate 2003 78,79 ..but techtud marked it as wrong..this qs has only one confusion which is how to use page table walk and tlb update...I used it in the part of L3 ache miss of Tlb miss.. and used this formula . ... hit(cache time) + L2 miss( L3 hit (cache time) + L3 miss(cache time+page table walk and Tlb update )))) Sir,pls check this
@Arjun sir, I solved it by using the same concept of gate 2003 78,79 ..but techtud marked it as wrong..this qs has only one confusion which is how to use page table walk ...
resuscitate
1.3k
views
resuscitate
asked
Jan 27, 2016
CO and Architecture
translation-lookaside-buffer
co-and-architecture
cache-memory
+
–
0
votes
2
answers
68
Find TLB Hit Ratio
Suppose TLB used in one level paging system with each look-up time of TLB 40 msec. Memory reference takes 120 msec. If the effective memory reference time is 180 msec then page table references are found in TLB is ______ Answer Given in booklet (0.833)
Suppose TLB used in one level paging system with each look-up time of TLB 40 msec. Memory reference takes 120 msec. If the effective memory reference time is 180 msec the...
pC
3.8k
views
pC
asked
Jan 25, 2016
CO and Architecture
co-and-architecture
translation-lookaside-buffer
+
–
4
votes
1
answer
69
which is accessed frist TLB or cache?
I have a doubt which is accessed first TLB or cache? I think answer should be TLB as we need it for address translation to get frame no. and then access cache Is my approach right?
I have a doubt which is accessed first TLB or cache?I think answer should be TLB as we need it for address translation to get frame no. and then access cacheIs my approac...
UK
1.7k
views
UK
asked
Dec 16, 2015
Operating System
operating-system
translation-lookaside-buffer
cache-memory
paging
+
–
Page:
« prev
1
2
3
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register
