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Machine instructions and Addressing modes. ALU, data‐path and control unit. Instruction pipelining. Memory hierarchy: cache, main memory and secondary storage; I/O interface (Interrupt and DMA mode)

$$\small{\overset{{\large{\textbf{Mark Distribution in Previous GATE}}}}{\begin{array}{|c|c|c|c|c|c|c|c|}\hline
\textbf{Year}&\textbf{2019}&\textbf{2018}&\textbf{2017-1}&\textbf{2017-2}&\textbf{2016-1}&\textbf{2016-2}&\textbf{Minimum}&\textbf{Average}&\textbf{Maximum}
\\\hline\textbf{1 Mark Count}&2&2&2&0&1&1&0&1.3&2
\\\hline\textbf{2 Marks Count}&1&3&4&3&2&5&1&3&5
\\\hline\textbf{Total Marks}&4&8&10&6&5&11&\bf{4}&\bf{7.3}&\bf{11}\\\hline
\end{array}}}$$

Questions without answers in CO and Architecture

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1
Which of the following is false? Interrupts which are initiated by an instruction are software interrupts When a subroutine is called, the address of the instruction following the CALL instruction is stored in the stack pointer A micro program which is written as $0$’s and $1$’s is a binary micro program None of the options
asked Mar 30 in CO and Architecture Lakshman Patel RJIT 69 views
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2
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3
A computer has a three-stage pipeline as shown in Fig. 1-7(a). On each clock cycle, one new instruction is fetched from memory at the address pointed to by the PC and put into the pipeline and the PC advanced. Each instruction occupies exactly ... stage and the first instruction of the interrupt handler is fetched into the pipeline. Does this machine have precise interrupts? Defend your answer.
asked Oct 28, 2019 in CO and Architecture Lakshman Patel RJIT 175 views
–1 vote
0 answers
4
#include <stdio.h> int main() { unsigned char arr[2] = {0x01, 0x00}; unsigned short int x = *(unsigned short int *) arr; printf("%d", x); getchar(); return 0; } Output in little endian and big endian ? Please someone provide a detailed explanation if possible with diagram.
asked Jun 9, 2019 in CO and Architecture Kushagra गुप्ता 127 views
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5
In a microprocessor, size of register is generally: Lesser than the size of the data it operates on Greater than the size of the data it operates on Equal to the size of the data it operates on
asked May 29, 2019 in CO and Architecture manikgupta123 258 views
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6
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7
How to find number of stall cycles and branch penalty & CPI in a branched instruction pipelining?
asked May 21, 2019 in CO and Architecture Ritabrata Dey 101 views
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0 answers
8
Block set associative cache consists of a total of 64blocks divided into 4blocks sets .The main memory contains 4096blocks ,each consisting of 128 words. how many bits for Main memory how many bits for TAG,SET,WORD . solution: MM=block size*words 2^12 * 2^7=19 bits TAG=9 SET=4 WORD=6 is this correct method or not please correct me
asked May 13, 2019 in CO and Architecture altamash 61 views
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0 answers
9
A memory system of size 16 kbytes is required to be designed using memory chips which have 12 address lines and 4 data lines each. No of chips required to design the memory system ______. Please provide a detailed solution.
asked May 7, 2019 in CO and Architecture Tuhin Dutta 323 views
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10
To get branch address, do we need base register value or Program Counter value?
asked Apr 17, 2019 in CO and Architecture srestha 105 views
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11
What is the concept of branch penalty , stall cycle and branch instructions and what are the formulas to get those ?? Someone please guide me..i am really facing much difficulty in these concepts while solving prev yr gate questions.
asked Apr 16, 2019 in CO and Architecture Ritabrata Dey 51 views
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0 answers
12
In Matrix Multiplication Operation Code uses Temporal Locality and Data uses Spatial Locality Data uses Temporal Locality and Code uses Spatial Locality Both data and code uses Spatial Locality Both data and code uses Temporal Locality
asked Apr 14, 2019 in CO and Architecture ved 32 views
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0 answers
13
Microprogrammed control Unit is useful when very small programs are to be run. Shouldn’t this statement be true because microprogrammed approach uses decoder, which slows down speed, so large programs would take more time, and small ones less?
asked Apr 12, 2019 in CO and Architecture Miny 32 views
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14
Register $R_{1}$ and $R_{2}$ of a computer contain the decimal values $1200$ and $4600$ . What is the effective address of the memory operand in each of the following instructions? $\left ( a \right )$ $Load$ $20\left ( R_{1} \right ),R_{5}$ ... $\left ( e \right )$ $Subtract$ $\left ( R_{1} \right )+,R_{5}$ Ans-1200//Autoincrement
asked Apr 2, 2019 in CO and Architecture srestha 133 views
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15
How do we perform 0 – 1 in 2’s complement subtraction using 1-bit register??
asked Mar 21, 2019 in CO and Architecture Doraemon 84 views
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16
Please can anyone help me how to measure the CPU Performance and everything related with it.
asked Mar 20, 2019 in CO and Architecture Devshree Dubey 115 views
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17
how is this executed MOV X, R ; μ[x]←R using IF, ID, OF,PO, WB
asked Mar 18, 2019 in CO and Architecture Doraemon 92 views
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0 answers
18
How to improve cache hit rate in case of transfer of element from 2-D array to matrix.? (Consider the column major order in 2D array)
asked Mar 17, 2019 in CO and Architecture Anuranjan 27 views
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0 answers
19
Can someone please provide a link to an article or a video explaining cache and arrays concept. Im having a hard time understanding that concept.
asked Mar 16, 2019 in CO and Architecture amitqy 53 views
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0 answers
20
Show how to do the following statement c = a[2] + b[0] a) using register direct, imm, register indirect b) using register direct, imm, absolute addressing c) using register direct, imm, register indirect with displacement
asked Mar 13, 2019 in CO and Architecture manisha11 64 views
1 vote
0 answers
21
When using pipelining can we have an arrangement like this? I1 F1 D1 E1 M1 W1 I2 F2 ______ ____ _____ D2 E2 M2 W2 I3 F3 D3 E3 M3 W3 Where I2 has Read after write dependency on I1 and operand forwarding is not used. I3 is independent of I1 and I2 F=INSTRUCTION FETCH. D=DECODING AND READING THE OPERANDS FROM THE REGISTER E=EXECUTE M=MEMORY OPERATION W=WRITE BACK
asked Feb 18, 2019 in CO and Architecture DIYA BASU 101 views
0 votes
0 answers
22
What is the difference between Multicore Processing and Parallel processing given that in both tasks/operations are performed simultaneously?
asked Feb 13, 2019 in CO and Architecture Reshu $ingh 82 views
0 votes
0 answers
23
what is (120)base 10=( ? )base 64 ??
asked Feb 4, 2019 in CO and Architecture DIYA BASU 114 views
0 votes
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24
Why we do right shift in booth algorithm? I know the working of booths algorithm. Suppose we have multiplicand M = 01011 and multiplier Q = 01110 We can write Q as (2^4 - 2^1). So multiplication reduces to 2^4(M) + 2(-M) Now booths algorithm rules are:- If Q = 0 ... which is 2^4(M) + 2(-M) we multiply by 16 and 2 which requires left shift. So how is booths algorithm working with right shift ?
asked Feb 4, 2019 in CO and Architecture kd..... 263 views
0 votes
0 answers
25
https://gateoverflow.in/2308/gate1993-11 This question can also be solved as a probability question where the random space contains (M1),(M1,M2),(M1,M2,M3) and let X be the random variable which gives the time for any of the three options selected from the sample space and correspondingly we give the PMF for each time selected and then we find the expectation?? Am I correct with my logic??
asked Feb 2, 2019 in CO and Architecture DIYA BASU 47 views
0 votes
0 answers
26
A computer has 64 bit instruction and 8 bit address.if there are 32 no of 3 address instruction and 248 no of 2 address instruction.how many 1 address instruction possible??
asked Feb 2, 2019 in CO and Architecture Ssgmailcom 66 views
2 votes
0 answers
27
A hypothetical processor on cache read miss requires one clock to send an address to Main Memory (MM) and eight clock cycles to access a 64-bit word from MM to processor cache. Miss rate of read is decreased from 14.8% to 2.6% when line size of cache ... words. The speed up of processor is achieved in dealing with average read miss after increasing the line size is_____ (Upto 2 decimal places)
asked Feb 1, 2019 in CO and Architecture newdreamz a1-z0 174 views
0 votes
0 answers
28
Please tell what happens to hit rate, hit time, compulsory miss rate, conflict miss rate, capacity miss rate, miss time on : 1. Increasing Cache size 2. Increasing Block size 3. Increasing number of lines 4. Increasing Associativity
asked Jan 31, 2019 in CO and Architecture Balaji Jegan 105 views
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29
I know the acess time to a sequential acess cache is given as Hitrate*(Cache acess time)+ Miss rate*(Cachec acess time + Mem acess time) Now in question if they explicitly say “ in case of miss data is obtained from memory and put into cache and again acessed from it”, will my formula change Hirate(Cache acess time)+ Misseate* ( Cache acess time+ Mem acess time + Cache acess time) pls help me
asked Jan 31, 2019 in CO and Architecture Aravind Adithya 1 33 views
0 votes
0 answers
30
Consider a 2 way set associative cache with 4 blocks. The memory block requests in the order. 4,6,3,8,5,6,0,15,6,17,20,15,0,8 If LRU is used for block replacement then memory set 17 will be in the cache block ____. (PS: the given answer is 1)
asked Jan 28, 2019 in CO and Architecture snaily16 208 views
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