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Recent activity by Aalok8523
5
answers
1
GATE CSE 2012 | Question: 1
Consider the following logical inferences. $I_{1}$: If it rains then the cricket match will not be played. The cricket match was played. Inference: There was no rain. $I_{2}$: If it rains then the cricket match will not be played. It did not rain. Inference: ... $I_{2}$ is a correct inference Both $I_{1}$ and $I_{2}$ are not correct inferences
Consider the following logical inferences.$I_{1}$: If it rains then the cricket match will not be played.The cricket match was played.Inference: There was no rain.$I_{2}...
9.0k
views
commented
Sep 1, 2020
Mathematical Logic
gatecse-2012
mathematical-logic
easy
logical-reasoning
+
–
10
answers
2
GATE CSE 2019 | Question: 35
Consider the first order predicate formula $\varphi$: $\forall x [ ( \forall z \: z | x \Rightarrow (( z=x) \vee (z=1))) \rightarrow \exists w ( w > x) \wedge (\forall z \: z | w \Rightarrow ((w=z) \vee (z=1)))]$ Here $a \mid b$ denotes ... of all integers Which of the above sets satisfy $\varphi$? $S_1$ and $S_2$ $S_1$ and $S_3$ $S_2$ and $S_3$ $S_1, S_2$ and $S_3$
Consider the first order predicate formula $\varphi$:$\forall x [ ( \forall z \: z | x \Rightarrow (( z=x) \vee (z=1))) \rightarrow \exists w ( w x) \wedge (\forall z \:...
19.8k
views
commented
Aug 25, 2020
Mathematical Logic
gatecse-2019
engineering-mathematics
discrete-mathematics
mathematical-logic
first-order-logic
2-marks
+
–
8
answers
3
GATE CSE 2017 Set 1 | Question: 02
Consider the first-order logic sentence $F:\forall x(\exists yR(x,y))$. Assuming non-empty logical domains, which of the sentences below are implied by $F$? $\exists y(\exists xR(x,y))$ $\exists y(\forall xR(x,y))$ $\forall y(\exists xR(x,y))$ $¬\exists x(\forall y¬R(x,y))$ IV only I and IV only II only II and III only
Consider the first-order logic sentence $F:\forall x(\exists yR(x,y))$. Assuming non-empty logical domains, which of the sentences below are implied by $F$?$\exists y(\ex...
17.1k
views
commented
Aug 25, 2020
Mathematical Logic
gatecse-2017-set1
mathematical-logic
first-order-logic
+
–
6
answers
4
GATE CSE 2014 Set 1 | Question: 1
Consider the statement "Not all that glitters is gold Predicate glitters$(x)$ is true if $x$ glitters and predicate gold$(x)$ is true if $x$ ... $\exists x: \text{glitters}(x)\wedge \neg \text{gold}(x)$
Consider the statement "Not all that glitters is gold”Predicate glitters$(x)$ is true if $x$ glitters and predicate gold$(x)$ is true if $x$ is gold. Which one of the ...
6.5k
views
commented
Aug 24, 2020
Mathematical Logic
gatecse-2014-set1
mathematical-logic
first-order-logic
+
–
4
answers
5
GATE CSE 1991 | Question: 15,b
Consider the following first order formula: ... Does it have finite models? Is it satisfiable? If so, give a countable model for it.
Consider the following first order formula:$\left ( \matrix{ \forall x \exists y : R(x,y) \\[1em] \Large \land \\[1em] \forall x \forall y : \left ( R(x,y) \impl...
6.2k
views
commented
Aug 22, 2020
Mathematical Logic
gate1991
mathematical-logic
first-order-logic
descriptive
+
–
4
answers
6
GATE CSE 1989 | Question: 14a
Symbolize the expression "Every mother loves her children" in predicate logic.
Symbolize the expression "Every mother loves her children" in predicate logic.
5.7k
views
commented
Aug 22, 2020
Mathematical Logic
gate1989
descriptive
first-order-logic
mathematical-logic
+
–
4
answers
7
GATE CSE 2005 | Question: 42
Let $R$ and $S$ be any two equivalence relations on a non-empty set $A$. Which one of the following statements is TRUE? $R$ $∪$ $S$, $R$ $∩$ $S$ are both equivalence relations $R$ $∪$ $S$ is an equivalence relation $R$ $∩$ $S$ is an equivalence relation Neither $R$ $∪$ $S$ nor $R$ $∩$ $S$ are equivalence relations
Let $R$ and $S$ be any two equivalence relations on a non-empty set $A$. Which one of the following statements is TRUE?$R$ $∪$ $S$, $R$ $∩$ $S$ are both equivalence r...
9.0k
views
commented
Aug 22, 2020
Set Theory & Algebra
gatecse-2005
set-theory&algebra
normal
relations
+
–
2
answers
8
GATE CSE 1995 | Question: 1.2
Which of the following statements is true? ROM is a Read/Write memory PC points to the last instruction that was executed Stack works on the principle of LIFO All instructions affect the flags
Which of the following statements is true?ROM is a Read/Write memoryPC points to the last instruction that was executedStack works on the principle of LIFOAll instruction...
4.7k
views
commented
Aug 18, 2020
CO and Architecture
gate1995
co-and-architecture
normal
instruction-execution
+
–
12
answers
9
GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two...
22.4k
views
commented
Aug 16, 2020
CO and Architecture
gatecse-2016-set2
co-and-architecture
data-path
normal
numerical-answers
+
–
5
answers
10
GATE CSE 2015 Set 3 | Question: 51
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$ ... $} & & & \text{$X$} & \\\hline \end{array}$ The minimum average latency (MAL) is ______
Consider the following reservation table for a pipeline having three stages $S_1, S_2 \text{ and } S_3$.$$\begin{array}{|ccccc|} \hline \textbf{Time} \rightarrow \\\hline...
40.8k
views
commented
Aug 15, 2020
CO and Architecture
gatecse-2015-set3
co-and-architecture
pipelining
difficult
numerical-answers
+
–
4
answers
11
GATE IT 2008 | Question: 40
A non pipelined single cycle processor operating at $100\;\text{MHz}$ is converted into a synchronous pipelined processor with five stages requiring $2.5\;\text{nsec}, 1.5\;\text{nsec}, 2\;\text{nsec}, 1.5\;\text{nsec}$ and $2.5\;\text{nsec}$, respectively ... $4.5$ $4.0$ $3.33$ $3.0$
A non pipelined single cycle processor operating at $100\;\text{MHz}$ is converted into a synchronous pipelined processor with five stages requiring $2.5\;\text{nsec}, ...
13.6k
views
commented
Aug 14, 2020
CO and Architecture
gateit-2008
co-and-architecture
pipelining
normal
+
–
2
answers
12
GATE IT 2005 | Question: 49
An instruction set of a processor has $125$ signals which can be divided into $5$ groups of mutually exclusive signals as follows: Group $1$ $:$ $20$ signals, Group $2$ $:$ $70$ signals, Group $3$ $:$ $2$ signals, Group $4$ ... signals. How many bits of the control words can be saved by using vertical microprogramming over horizontal microprogramming? $0$ $103$ $22$ $55$
An instruction set of a processor has $125$ signals which can be divided into $5$ groups of mutually exclusive signals as follows:Group $1$ $:$ $20$ signals, Group $2$ $:...
9.2k
views
commented
Aug 12, 2020
CO and Architecture
gateit-2005
co-and-architecture
microprogramming
normal
+
–
3
answers
13
GATE CSE 1997 | Question: 5.3
A micro instruction is to be designed to specify: none or one of the three micro operations of one kind and none or upto six micro operations of another kind The minimum number of bits in the micro-instruction is: $9$ $5$ $8$ None of the above
A micro instruction is to be designed to specify:none or one of the three micro operations of one kind andnone or upto six micro operations of another kindThe minimum num...
11.3k
views
commented
Aug 12, 2020
CO and Architecture
gate1997
co-and-architecture
microprogramming
normal
+
–
1
answer
14
GATE CSE 1990 | Question: 8a
A single bus CPU consists of four general purpose register, namely, $R0, \ldots, R3, \text{ALU}, \text{MAR}, \text{MDR}, \text{PC}, \text{SP}$ and $\text{IR}$ (Instruction Register). Assuming suitable microinstructions, write a microroutine for the instruction, $\text{ADD }R0, R1$.
A single bus CPU consists of four general purpose register, namely, $R0, \ldots, R3, \text{ALU}, \text{MAR}, \text{MDR}, \text{PC}, \text{SP}$ and $\text{IR}$ (Instructio...
2.0k
views
commented
Aug 11, 2020
CO and Architecture
gate1990
descriptive
co-and-architecture
data-path
+
–
3
answers
15
GATE CSE 1987 | Question: 4a
Find out the width of the control memory of a horizontal microprogrammed control unit, given the following specifications: $16$ control lines for the processor consisting of ALU and $7$ registers. Conditional branching facility by checking $4$ status bits. Provision to hold $128$ words in the control memory.
Find out the width of the control memory of a horizontal microprogrammed control unit, given the following specifications:$16$ control lines for the processor consisting ...
5.6k
views
commented
Aug 11, 2020
CO and Architecture
gate1987
co-and-architecture
microprogramming
descriptive
+
–
4
answers
16
GATE CSE 1994 | Question: 12
Assume that a CPU has only two registers $R_1$ and $R_2$ and that only the following instruction is available $XOR \: R_i, R_j;\{R_j \leftarrow R_i \oplus R_j, \text{ for } i, j =1, 2\}$ Using this XOR instruction, find an instruction sequence in ... and $R_2$ The line p of the circuit shown in figure has stuck at $1$ fault. Determine an input test to detect the fault.
Assume that a CPU has only two registers $R_1$ and $R_2$ and that only the following instruction is available $XOR \: R_i, R_j;\{R_j \leftarrow R_i \oplus R_j, \text{ for...
3.8k
views
commented
Jul 31, 2020
CO and Architecture
gate1994
co-and-architecture
machine-instruction
normal
descriptive
+
–
1
answer
17
GATE CSE 2007 | Question: 10
Consider a $4$-way set associative cache consisting of $128$ lines with a line size of $64$ words. The CPU generates a $20-bit$ address of a word in main memory. The number of bits in the TAG, LINE and WORD fields are respectively: $9, 6, 5$ $7, 7, 6$ $7, 5, 8$ $9, 5, 6$
Consider a $4$-way set associative cache consisting of $128$ lines with a line size of $64$ words. The CPU generates a $20-bit$ address of a word in main memory. The numb...
13.0k
views
commented
Jul 22, 2020
CO and Architecture
gatecse-2007
co-and-architecture
cache-memory
normal
+
–
2
answers
18
GATE IT 2006 | Question: 42
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is: $32$ $ns$ $64$ $ns$ $96$ $ns$ $128$ $ns$
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is:$...
11.7k
views
commented
Jul 22, 2020
CO and Architecture
gateit-2006
co-and-architecture
cache-memory
normal
+
–
5
answers
19
GATE CSE 2006 | Question: 74
Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but direct mapped. The size of an address is $32\; \text{bits}$ in both cases . A $2\text{-to-}1$ multiplexer has ... The value of $h_1$ is: $2.4 \text{ ns} $ $2.3 \text{ ns}$ $1.8 \text{ ns}$ $1.7 \text{ ns}$
Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but dire...
28.6k
views
commented
Jul 20, 2020
CO and Architecture
gatecse-2006
co-and-architecture
cache-memory
normal
+
–
5
answers
20
GATE IT 2005 | Question: 61
Consider a $2$-way set associative cache memory with $4$ sets and total $8$ cache blocks $(0-7)$ and a main memory with $128$ blocks $(0-127)$. What memory blocks will be present in the cache after the following sequence of memory block references if LRU policy is used for cache block replacement. ... $9$ $16$ $55$ $0$ $5$ $7$ $9$ $16$ $55$ $3$ $5$ $7$ $9$ $16$ $55$
Consider a $2$-way set associative cache memory with $4$ sets and total $8$ cache blocks $(0-7)$ and a main memory with $128$ blocks $(0-127)$. What memory blocks will be...
8.9k
views
commented
Jul 20, 2020
CO and Architecture
gateit-2005
co-and-architecture
cache-memory
normal
+
–
6
answers
21
GATE CSE 1993 | Question: 11
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$ ... a page swap is $T_i$. Calculate the average time $t_A$ required for a processor to read one word from this memory system.
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$.$$\begin{array}{|c|c|c|c|} \hli...
10.8k
views
commented
Jul 19, 2020
CO and Architecture
gate1993
co-and-architecture
cache-memory
normal
descriptive
+
–
2
answers
22
GATE IT 2006 | Question: 57
The wait and signal operations of a monitor are implemented using semaphores as follows. In the following, $x$ is a condition variable, mutex is a semaphore initialized to $1$, $x$_sem is a semaphore initialized to $0$, $x$_count is the number of processes waiting on semaphore $x$_sem, ... $V(next), P(x\_sem)$ $P(next), V(x\_sem)$ $P(x\_sem), V(x\_sem)$
The wait and signal operations of a monitor are implemented using semaphores as follows. In the following,$x$ is a condition variable,mutex is a semaphore initialized to ...
6.4k
views
commented
Jul 16, 2020
Operating System
gateit-2006
operating-system
process-synchronization
semaphore
normal
+
–
4
answers
23
GATE CSE 1998 | Question: 24
Four jobs are waiting to be run. Their expected run times are $6, 3, 5$ and $x.$ In what order should they be run to minimize the average response time? Write a concurrent program using $\text{par begin-par end}$ to represent the precedence graph shown below.
Four jobs are waiting to be run. Their expected run times are $6, 3, 5$ and $x.$ In what order should they be run to minimize the average response time?Write a concurrent...
12.0k
views
commented
Jul 15, 2020
Operating System
gate1998
operating-system
process-scheduling
descriptive
+
–
4
answers
24
GATE CSE 1998 | Question: 1.29
Which of the following is an example of a spooled device? The terminal used to enter the input data for the C program being executed An output device used to print the output of a number of jobs The secondary memory device in a virtual storage system The swapping area on a disk used by the swapper
Which of the following is an example of a spooled device?The terminal used to enter the input data for the C program being executedAn output device used to print the outp...
4.7k
views
commented
Jul 14, 2020
Operating System
gate1998
operating-system
io-handling
easy
+
–
16
answers
25
GATE IT 2007 | Question: 83
The head of a hard disk serves requests following the shortest seek time first (SSTF) policy. What is the maximum cardinality of the request set, so that the head changes its direction after servicing every request if the total number of tracks are $2048$ and the head can start from any track? $9$ $10$ $11$ $12$
The head of a hard disk serves requests following the shortest seek time first (SSTF) policy. What is the maximum cardinality of the request set, so that the head changes...
22.8k
views
commented
Jul 11, 2020
Operating System
gateit-2007
operating-system
disk-scheduling
normal
+
–
5
answers
26
GATE CSE 2014 Set 2 | Question: 20
A FAT (file allocation table) based file system is being used and the total overhead of each entry in the FAT is $4$ bytes in size. Given a $100 \times 10^6$ bytes disk on which the file system is stored and data block size is $10^3$ bytes, the maximum size of a file that can be stored on this disk in units of $10^6$ bytes is _________.
A FAT (file allocation table) based file system is being used and the total overhead of each entry in the FAT is $4$ bytes in size. Given a $100 \times 10^6$ bytes disk o...
20.5k
views
commented
Jul 10, 2020
Operating System
gatecse-2014-set2
operating-system
disk
numerical-answers
normal
file-system
+
–
2
answers
27
GATE CSE 1991 | Question: 11,b
Consider the following scheme for implementing a critical section in a situation with three processes $P_i, P_j$ and $P_k$. Pi; repeat flag[i] := true; while flag [j] or flag[k] do case turn of j: if flag [j] then begin flag ... in which a waiting process can never enter the critical section? If so, explain and suggest modifications to the code to solve this problem
Consider the following scheme for implementing a critical section in a situation with three processes $P_i, P_j$ and $P_k$.Pi;repeat flag[i] := true; while flag [j] or fl...
2.0k
views
commented
Jul 10, 2020
Operating System
gate1991
process-synchronization
normal
operating-system
descriptive
+
–
5
answers
28
GATE CSE 1998 | Question: 25b
Consider a disk with $c$ cylinders, $t$ tracks per cylinder, $s$ sectors per track and a sector length $s_l$. A logical file $d_l$ with fixed record length $r_l$ is stored continuously on this disk starting at location $(c_L, t_L, s_L)$, where ... the formula to calculate the disk address (i.e. cylinder, track and sector) of a logical record n assuming that $r_l=s_l$.
Consider a disk with $c$ cylinders, $t$ tracks per cylinder, $s$ sectors per track and a sector length $s_l$. A logical file $d_l$ with fixed record length $r_l$ is stor...
2.9k
views
commented
Jul 7, 2020
Operating System
gate1998
operating-system
disk
descriptive
+
–
3
answers
29
GATE CSE 1998 | Question: 2-9
Formatting for a floppy disk refers to arranging the data on the disk in contiguous fashion writing the directory erasing the system data writing identification information on all tracks and sectors
Formatting for a floppy disk refers toarranging the data on the disk in contiguous fashionwriting the directoryerasing the system datawriting identification information o...
7.3k
views
commented
Jul 7, 2020
Operating System
gate1998
operating-system
disk
normal
+
–
2
answers
30
GATE CSE 1997 | Question: 74
A program $P$ reads and processes $1000$ consecutive records from a sequential file $F$ stored on device $D$ without using any file system facilities. Given the following Size of each record $= 3200$ bytes Access time of $D = 10$ ... a blocking factor of $2$ (i.e., each block on $D$ contains two records of $F$) and $P$ uses one buffer?
A program $P$ reads and processes $1000$ consecutive records from a sequential file $F$ stored on device $D$ without using any file system facilities. Given the following...
7.5k
views
commented
Jul 7, 2020
Operating System
gate1997
operating-system
disk
+
–
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