Recent activity by Amit.kumar / GATE Overflow for GATE CSE

3 answers

1

ISRO2014-34
How much memory is required to implement $z$-buffer algorithm for a $512 \times 512 \times 24$ bit-plane image? $768$ KB $1$ MB $1.5$ MB $2$ MB

How much memory is required to implement $z$-buffer algorithm for a $512 \times 512 \times 24$ bit-plane image?$768$ KB$1$ MB$1.5$ MB$2$ MB

5.3k views

answered Apr 6, 2018

1 answer

2

Pipeline

343 views

answered Jun 9, 2017

2 answers

3

carl Hamacher 6th edition Q.no 5.11
A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows: Branch 20% Load 20% Store 10% Computational instructions 50% Estimate the rate of instruction ... clock cycles. On average, access to the data operands of a Load or Store instruction is completed in 3 clock cycles.

A RISC processor that uses the five-step sequence in Figure 5.4 is driven by a 1-GHz clock. Instruction statistics in a large program are as follows:Branch 20%Load 20%Sto...

1.6k views

asked Jun 7, 2017

1 answer

4

PipeLine

1.2k views

commented Jun 5, 2017

0 answers

5

Pipelining Doubt
I1: L R0, loc 1; R0 <= M[loc1] I2: A R0, R0; R0 <= R0 +R0 WB of I1 and ID stage of I2....should be overlapping or not? How to consider this case...as in gate previous questions answers are changing according to the given options?

I1: L R0, loc 1; R0 <= M[loc1]I2: A R0, R0; R0 <= R0 +R0 WB of I1 and ID stage of I2....should be overlapping or not?How to consider this case...as in gate previou...

255 views

commented Jun 5, 2017

1 answer

6

MadeEasy Subject Test: CO & Architecture - Pipelining

456 views

commented Jun 5, 2017

2 answers

7

MadeEasy Test Series: CO & Architecture - Pipelining
Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being branch. The value of X such that speedup is atleast 5 is ________ ? ------------ ... 5 => 1200 = 1040 - 15X => 15X = - 160 Which is not possible. Where am I going wrong ?? :

Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being b...

1.1k views

commented Jun 4, 2017

1 answer

8

pipeline bypassing
A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, OF and WO stages takes 1 clock cycle each for any instruction. The PO ... number of clock cycles needed to execute the following sequence of instruction where operand forwarding from WO to PO and PO to OF is used

A 5 stage pipelined processor has instruction fetch (IF), operand fetch (OF). Instruction decode (ID), perform operation (PO) and Write operand (WO) stages. The IF, ID, O...

2.2k views

commented Jun 1, 2017

4 answers

9

GATE CSE 2015 Set 2 | Question: 44
Consider the sequence of machine instruction given below: ... forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instruction is _________.

Consider the sequence of machine instruction given below:$$\begin{array}{ll} \text{MUL} & \text{R5, R0, R1} \\ \text{DIV} & \text{R6, R2, R3} \\ \text{ADD} & \text{R7,...

26.3k views

commented Jun 1, 2017

2 answers

10

Data Hazards [GateBook]

2.0k views

commented Jun 1, 2017

3 answers

11

Pipeline: Calculate average instruction execution time
An instruction pipeline has five stages with stage latencies 1 ns, 2ns, 5 ns, 2ns, and 0.5 ns, respectively. A program has 10% branch instructions which execute in the fourth stage and produce the next instruction pointer at the end of the fourth stage. Calculate the average instruction execution time:

An instruction pipeline has five stages with stage latencies 1 ns, 2ns, 5 ns, 2ns, and 0.5 ns, respectively. A program has 10% branch instructions which execute in the fo...

6.0k views

commented Jun 1, 2017

5 answers

12

ISI2012-PCB-CS-2a
A machine $\mathcal{M}$ has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses: $F$-stage - instruction fetch ($9$ ns), $D$-stage - instruction decode and register fetch ($3$ ns), $X$-stage ... $3$rd instruction needs a $1$ - cycle stall before the $X$-stage. Calculate the CPU time in seconds for completing $P$.

A machine $\mathcal{M}$ has the following five pipeline stages; their respective time requirements in nanoseconds (ns) are given within parentheses:$F$-stage — instruct...

2.6k views

commented Jun 1, 2017

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