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1
answer
1
IISc M.Tech Admission
When will IISc announce its First Round of Direct Admissions Offers for CSE ?? IIT Bombay will declare its result for direct admission on 17th April and demands fee submission by 23rd April. By that time, Will IISc have declared the Direct Admission Offers ?? What to ... IISc but need to apply for Bombay also (Safe Side) My CS 2018 GATE Rank is 67 and Birth Category is OBCNC.
answer edited
Jul 17, 2018
in
IISc/IITs

1.4k
views
iisc
admission
2
answers
2
Operating systems
Is preemotion possible when the process is in its critical section in the binary semaphores?
answered
Jul 10, 2018
in
Operating System

47
views
synchronizingmechanism
operatingsystem
7
answers
3
GATE20184
Let $\oplus$ and $\odot$ denote the Exclusive OR and Exclusive NOR operations, respectively. Which one of the following is NOT CORRECT? $\overline{P \oplus Q} = P \odot Q$ $\overline{P} \oplus Q = P \odot Q$ $\overline{P} \oplus \overline{Q} = P \oplus Q$ $P \oplus \overline{P} \oplus Q = ( P \odot \overline{P} \odot \overline{Q})$
edited
Apr 10, 2018
in
Digital Logic

2.5k
views
gate2018
digitallogic
normal
booleanalgebra
4
answers
4
GATE201813
Match the following: ... $\text{PII, QI, RIV, SIII}$ $\text{PIV, QI, RII, SIII}$ $\text{PIV, QI, RIII, SII}$
commented
Feb 14, 2018
in
Computer Networks

3k
views
gate2018
computernetworks
networklayering
normal
9
answers
5
GATE2017255
Consider the following C program. #include<stdio.h> #include<string.h> int main() { char* c=”GATECSIT2017”; char* p=c; printf(“%d”, (int)strlen(c+2[p]6[p]1)); return 0; } The output of the program is _______
commented
Jan 27, 2018
in
Programming

10k
views
gate20172
programminginc
numericalanswers
1
answer
6
Identify class of the language
L={ xy  x,y$\epsilon$ (a+b)*, na(x) = nb(y) }
answer selected
Jan 24, 2018
in
Theory of Computation

124
views
theoryofcomputation
1
answer
7
theory of computation
The minimum number of states needed for DFA of langauge L is ________.
commented
Jan 23, 2018
in
Theory of Computation

220
views
1
answer
8
Throughput
Find throughput...
answer selected
Jan 11, 2018
in
Operating System

115
views
1
answer
9
Ace Test series: Graph Theory  Graph Connectivity
Please can anyone tell whether my answer is wrong or solution provided by them is correct??
answered
Jan 8, 2018
in
Graph Theory

122
views
acetestseries
graphtheory
graphconnectivity
1
answer
10
ace test series
What is RTT ?? How can i solve?? wht is the ans.?
answered
Jan 1, 2018
in
Computer Networks

48
views
1
answer
11
Linear Algebra: Matrix operations
Consider two statements: 1) Eigenvalue of M = Eigenvalue of M' {M' is the matrix gets after row operation} 2) Eigenvalue of M $\lambda$I = Eigenvalue of M $\lambda$I' {M $\lambda$I' is the matrix gets after row operation}
answered
Jan 1, 2018
in
Linear Algebra

139
views
engineeringmathematics
linearalgebra
eigenvalue
1
answer
12
which one to choose for full length tests? Tests from test series or previous year questions?
answered
Jan 1, 2018
in
Others

116
views
preparation
1
answer
13
doubt
(R*)^0 = λ right ?
answered
Jan 1, 2018
in
Theory of Computation

49
views
1
answer
14
Cycle
commented
Jan 1, 2018
in
Graph Theory

128
views
0
answers
15
Does Load and Store instruction Require ALU Operation ?
Does Load and Store instruction Require ALU Operation ?
asked
Jan 1, 2018
in
CO and Architecture

59
views
coandarchitecture
1
answer
16
Syllogism
$Problem\ 1\\(A)\ Sehwag\ is\ a\ good\ batsman.\\(B)\ Batsmen\ are\ physically\ powerful.\\ Conclusion\\I.\ All\ physically\ powerful\ are\ Batsmen.\\ II.\ Sehwag\ is\ physically\ powerful\\ which\ of\ the\ above\ follows?$ ...
answered
Dec 29, 2017
in
Verbal Ability

395
views
generalaptitude
verbalability
syllogism
1
answer
17
complexityofparser
Consider the following statements: S1 : for LL(1) parsing of n tokens ,time complexity in the best case is O(n) and worst case is O(n4) . S2 : for LR parsing of n tokens ,time complexity in the best case is O(n) and worst case is O(n3) . which of ... statements are true? a)Only S1 is correct. b)Only S2 is correct. c) Both S1 and S2 is correct. d)Neither S1 nor S2 is correct.
commented
Dec 28, 2017
in
Compiler Design

1.3k
views
4
answers
18
GATE19901iva
A 32bit floatingpoint number is represented by a 7bit signed exponent, and a 24bit fractional mantissa. The base of the scale factor is 16, The range of the exponent is ___________
answer edited
Dec 27, 2017
in
Digital Logic

2.9k
views
gate1990
descriptive
digitallogic
numberrepresentation
floatingpointrepresentation
1
answer
19
We have 2 Schedule S1 and S2 ... There are no Conflict Operation in S1 and S2.
We have 2 Schedule S1 and S2 ... There are no Conflict Operation in S1 and S2. So can we say they are conflict equivalent ?
asked
Dec 27, 2017
in
Databases

169
views
databases
transactions
0
answers
20
Conflict equivalent
asked
Dec 26, 2017
in
Databases

159
views
databases
conflictserializable
concurrency
2
answers
21
Carry lookahead adder
can anyone tell me wat is the right equation for carry generator in carry lookahead adder ?? Confused .. $ C_{i} = G_{i}+P_{i}C_{i1}$ $ C_{i+1}=G_{}i+P_{}iC_{}i$
commented
Dec 19, 2017
in
Digital Logic

282
views
digitallogic
lookaheadadder
carrygenerator
2
answers
22
MCQmade_eassay
How many full adder are needed to construct mbit parallel adder ? A. m/2 B. m C. m1 D. m+1
answered
Dec 14, 2017
in
Digital Logic

773
views
full_adder
parallel_aader
0
answers
23
Find Min. Number of Temperory Variables ?
commented
Dec 8, 2017
in
Compiler Design

77
views
0
answers
24
Can we use synchronous counter to divide freq.
Can we use synchronous counter to divide frequency?
asked
Nov 25, 2017
in
Digital Logic

51
views
digitallogic
2
answers
25
what is the meaning of probe sequence in hashing ?
I am unable to understand the meaning of probe sequence in context of no of slots , I have seen questions like no of probe sequences possible in quadratic or linear probing is m while in double hashing it is m^2 , so what is the ... sequence , is it that once collision occurs , so now to which index will the key would be next mapped on to ?
answer selected
Nov 10, 2017
in
DS

2k
views
7
answers
26
GATE2015349
Suppose $c = \langle c[0], \dots, c[k1]\rangle$ is an array of length $k$, where all the entries are from the set $\{0, 1\}$. For any positive integers $a \text{ and } n$, consider the following pseudocode. DOSOMETHING (c, a, n) $z \leftarrow 1$ ... , then the output of DOSOMETHING(c, a, n) is _______.
commented
Nov 9, 2017
in
Algorithms

2.6k
views
gate20153
algorithms
identifyfunction
normal
numericalanswers
1
answer
27
MadeEasy Subject Test: CO & Architecture  Addressing Modes
asked
Nov 8, 2017
in
CO and Architecture

206
views
coandarchitecture
addressingmodes
madeeasytestseries
1
answer
28
Testbook Chapter for Cache Memory
answer selected
Nov 3, 2017
in
CO and Architecture

111
views
cachememory
4
answers
29
GATE201413
Let $G=(V,E)$ be a directed graph where $V$ is the set of vertices and $E$ the set of edges. Then which one of the following graphs has the same strongly connected components as $G$ ? $G_1$ = $(V,E_1)$ where $E_1 = \left\{(u,v) \mid (u,v) \notin E\right\}$ $G_2$ ... $\leq2$ from $u$ to $v$ in $E\}$ $G_4$ = $(V_4,E)$ where $V_4$ is the set of vertices in $G$ which are not isolated
commented
Oct 23, 2017
in
DS

5.4k
views
gate20141
datastructures
graphs
ambiguous
1
answer
30
SLR(1) or Not
Whether followingis SLR(1) or Not ? E>E+T/T T>TF/F F>F*/a/b Doubt : While making state you will get one state as I1(E'>E. & E>E.+T ) , is this shift reduce or not ? if not then while making parsing table for LR(0) what will you put in I1 state .... ( All Shift/Reduce Entry as Accept or not) ?
asked
Oct 23, 2017
in
Compiler Design

248
views
compilerdesign
parsing
Amazon.in Widgets
52,223
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