Login
Register
Dark Mode
Brightness
Profile
Edit Profile
Messages
My favorites
My Updates
Logout
Filter
Profile
Wall
Recent activity
All questions
All answers
Exams Taken
All Blogs
Answers by Bikram
1
votes
161
Self Doubt
Do commit operations matter while checking serilizability?If yes why?
Do commit operations matter while checking serilizability?If yes why?
522
views
answered
Jul 16, 2017
Databases
databases
transaction-and-concurrency
view-serializable
conflict-serializable
+
–
0
votes
162
Test by Bikram | Theory of Computation | Test 1 | Question: 30
Given a regular grammar $G_1$ and a context free grammar $G_2$, the problem of deciding if $L(G_1)$ is a proper subset of $L(G_2)$ is: Decidable Undecidable but semi-decidable Not even semi-decidable Indeterminable
Given a regular grammar $G_1$ and a context free grammar $G_2$, the problem of deciding if $L(G_1)$ is a proper subset of $L(G_2)$ is:DecidableUndecidable but semi-decida...
1.3k
views
answered
Jul 16, 2017
Theory of Computation
tbb-toc-1
+
–
0
votes
163
Gateforum Test
1-In self referential relation we alwasy need 1 table. 2-If there is a total participation of one entity with the relation,we can can merge E1,the relation and E2 into a single table. Which of the above given statements are true?
1-In self referential relation we alwasy need 1 table.2-If there is a total participation of one entity with the relation,we can can merge E1,the relation and E2 into a ...
463
views
answered
Jul 15, 2017
Databases
databases
er-diagram
+
–
1
votes
164
Is the TIME educational study material enough for GATE CS preparation?
Is the TIME educational study material enough for GATE CS preparation? I can solve general gate computer Science questions, but want more questions to practice. Also suggest any other institutes study material which focuses on variety of Questions instead of theoretical concepts.
Is the TIME educational study material enough for GATE CS preparation?I can solve general gate computer Science questions, but want more questions to practice.Also sugges...
508
views
answered
Jul 15, 2017
Study Resources
study-resources
+
–
1
votes
165
Test by Bikram | Databases | Test 1 | Question: 4
Each dealer owns one or more cars and each car is owned by at-most one dealer. If Dealer table has $20$ tuples and Cars table has $60$ tuples then owns table can have maximum _____ number of tuples
Each dealer owns one or more cars and each car is owned by at-most one dealer. If Dealer table has $20$ tuples and Cars table has $60$ tuples then owns table can have max...
754
views
answered
Jul 15, 2017
Databases
tbb-dbms-1
numerical-answers
+
–
2
votes
166
maximum value of n to be deadlock
A computer system has 6 tape drives, with n processes competing for them. Each process may need 3 tape drives. What is the maximum value of n for which the system is guaranteed to be deadlock? Justify your answer.
A computer system has 6 tape drives, with n processes competing for them. Each process may need 3 tape drives. What is the maximum value of n for which the system is guar...
3.0k
views
answered
Jul 14, 2017
Operating System
graph-theory
+
–
2
votes
167
MIN Resource requirement for deadlock
A system is having 3 user process , each requiring 2 units of resource R . WHAT IS the minimum and maximum no. of units of R required such that no deadlock will occur ?
A system is having 3 user process , each requiring 2 units of resource R . WHAT IS the minimum and maximum no. of units of R required such that no deadlock will occ...
4.0k
views
answered
Jul 14, 2017
Operating System
deadlock-prevention-avoidance-detection
operating-system
+
–
4
votes
168
Deadlock
Which is true/false & why 1.) There is a deadlock b/w 2 threads in a process ? 2.) Deadlock occurs with single resource ?
Which is true/false & why 1.) There is a deadlock b/w 2 threads in a process ?2.) Deadlock occurs with single resource ?
2.2k
views
answered
Jul 14, 2017
Operating System
deadlock-prevention-avoidance-detection
operating-system
+
–
9
votes
169
user and kernel mdoe
can anyone tell what are different activities that are performed in kernel mode user mode how to change frm user mode to kernel mode and vice-versa,,
can anyone tell what are different activities that are performed in kernel modeuser modehow to change frm user mode to kernel mode and vice-versa,,
2.5k
views
answered
Jul 14, 2017
Operating System
operating-system
threads
process
+
–
2
votes
170
user and kernel mdoe
can anyone tell what are different activities that are performed in kernel mode user mode how to change frm user mode to kernel mode and vice-versa,,
can anyone tell what are different activities that are performed in kernel modeuser modehow to change frm user mode to kernel mode and vice-versa,,
2.5k
views
answered
Jul 14, 2017
Operating System
operating-system
threads
process
+
–
2
votes
171
#threads
int main() { if(fork() == 0) printf("GATE2018"); if(fork() == 0) printf("GATE2018"); } How many times GATE2018 printed?
int main() { if(fork() == 0) printf("GATE2018"); if(fork() == 0) printf("GATE2018"); }How many times GATE2018 printed?
1.0k
views
answered
Jul 14, 2017
Operating System
process
threads
+
–
0
votes
172
#THREADS
if(fork() && fork()) { fork(); } if(fork()||fork()) { fork(); fork(); } printf("XYZ"); How many time XYZ gets printed ?
if(fork() && fork()) {fork();}if(fork()||fork()) {fork();fork();}printf("XYZ");How many time XYZ gets printed ?
864
views
answered
Jul 14, 2017
Operating System
process
threads
+
–
2
votes
173
what is meant by simultaneously access or hierarchial access in computer organisation?
482
views
answered
Jul 13, 2017
CO and Architecture
co-and-architecture
+
–
1
votes
174
binary representation
pls someone explain How to left shift this number ? 1010110<<2 Answer 1: shifting to the left means adding extra 0's as rightmost bits so in this case it means 101011000 now digit will be 1011000 but 1010110 represents 86 in decimal and left shift by 2 means multiply with 4 to the decimal number and now result 344 =101011000 now m confused ?
pls someone explainHow to left shift this number ?1010110<<2Answer 1: shifting to the left means adding extra 0's as rightmost bits so in this case it means 101011000 now...
854
views
answered
Jul 13, 2017
CO and Architecture
number-representation
+
–
1
votes
175
probability_sheldon ross
Which chapter is readable for GATE in A First Course In Probability(Sheldon Ross) Say with its subtopic in detail.....Thank For Answer
Which chapter is readable for GATE in A First Course In Probability(Sheldon Ross) Say with its subtopic in detail.....Thank For Answer
499
views
answered
Jul 13, 2017
Others
http
gateoverflow
in
ask
+
–
3
votes
176
Deadlock
1) How deadlock is an extreme case of starvation. 2) How deadlock avoidance is less restrictive than deadlock prevention.
1) How deadlock is an extreme case of starvation.2) How deadlock avoidance is less restrictive than deadlock prevention.
834
views
answered
Jul 13, 2017
22
votes
177
GATE CSE 2001 | Question: 1.8
Which of the following statements is false? Virtual memory implements the translation of a program's address space into physical memory address space Virtual memory allows each program to exceed the size of the primary memory Virtual memory increases the degree of multiprogramming Virtual memory reduces the context switching overhead
Which of the following statements is false?Virtual memory implements the translation of a program's address space into physical memory address spaceVirtual memory allows ...
21.6k
views
answered
Jul 13, 2017
Operating System
gatecse-2001
operating-system
virtual-memory
normal
+
–
1
votes
178
VIrtual Paging :Basic Question
If we say virtual address is 34 bit and we use 3 level page table. 12 bits page offset. first level page table =9 bits second level page table = 5 bits third level page table =8 bits. My question is in third level page table there is 2^8 entries what is meant by second level page and first level page table ? If possible please draw diagram .
If we say virtual address is 34 bit and we use 3 level page table.12 bits page offset.first level page table =9 bitssecond level page table = 5 bitsthird level page table...
488
views
answered
Jul 13, 2017
Operating System
virtual-memory
paging
+
–
1
votes
179
OS - Virtual Memory - Valid-Invalid Bit vs Modify Bit [DOUBT]
I am trying to understand the difference between the valid-invalid bit and the modify bit in paging My current understanding is that the valid invalid bit is in the page table and indicates whether that page has ... Is this a correct understanding? Particularly the locations where these are present? Any other insights are gladly accepted
I am trying to understand the difference between the valid-invalid bit and the modify bit in pagingMy current understanding is that the valid invalid bit is in the page t...
3.7k
views
answered
Jul 12, 2017
Operating System
operating-system
virtual-memory
paging
+
–
3
votes
180
The process of accessing data stored in a serial access memory is similar to manipulating data on a
The process of accessing data stored in a serial access memory is similar to manipulating data on a (A) heap (B) queue (C) stack (D) binary tree
The process of accessing data stored in a serial access memory is similar to manipulating data on a(A) heap (B) queue(C) stack ...
23.9k
views
answered
Jul 12, 2017
1
votes
181
Discrete Maths Rosen 6th Edition - Is the section 'proofs and strategy' part of the Gate syllabus?
Hi. I am new to Gate preparation. It would be very helpful if someone could clarify: Are Section 1.6 and 1.7 (Introduction to Proofs and Proof Methods and Strategy) from Kenneth Rosen (6th Edition) part of the Gate Syllabus? I didn't see them mentioned in the syllabus, hence asking. Thanks.
Hi.I am new to Gate preparation. It would be very helpful if someone could clarify:Are Section 1.6 and 1.7 (Introduction to Proofs and Proof Methods and Strategy) from Ke...
1.0k
views
answered
Jul 12, 2017
Mathematical Logic
kenneth-rosen
discrete-mathematics
syllabus
+
–
10
votes
182
Test by Bikram | Theory of Computation | Test 1 | Question: 13
An NFA has $10$ states out of which $3$ are final states. The maximum number of final states in converted DFA is: $895$ $894$ $896$ $897$
An NFA has $10$ states out of which $3$ are final states. The maximum number of final states in converted DFA is:$895$$894$$896$$897$
1.0k
views
answered
Jul 11, 2017
Theory of Computation
tbb-toc-1
+
–
4
votes
183
[DBMS] Number of view equal schedules
Number of schedules view equal to following schedule :- r1(A), w1(B), r2(A), w2(B), r3(A), w3(B)
Number of schedules view equal to following schedule :- r1(A), w1(B), r2(A), w2(B), r3(A), w3(B)
10.7k
views
answered
Jul 11, 2017
Databases
databases
view-serializable
transaction-and-concurrency
+
–
0
votes
184
Computing Effective Memory access time - Cache organization
Consider the following information about a hypothetical processor. Assume the cache is physically addressed TLBHit Rate: 95% access time 1 cycle Cache Hit Rate: 90% access time 1 cycle when tlb and cache both get miss, page fault rate 1% TLB access and ... 1 + .1(5+ .01(100) ) = 2.675 Could someone pls point out the flaw in the logic?
Consider the following information about a hypothetical processor.Assume the cache is physically addressedTLBHit Rate: 95% access time 1 cycleCache Hit Rate: 90% access t...
1.3k
views
answered
Jul 10, 2017
CO and Architecture
co-and-architecture
cache-memory
translation-lookaside-buffer
+
–
3
votes
185
Operating system concepts
Multi processing OS is an OS with more than one processor it it right?? if its is it implies that throughput is better is these os ans more no. of process can be excecuted per unit time.
Multi processing OS is an OS with more than one processor it it right?? if its is it implies that throughput is better is these os ans more no. of process can be excecute...
466
views
answered
Jul 9, 2017
Operating System
operating-system
process-scheduling
+
–
0
votes
186
MadeEasy Test Series: CO & Architecture - Cache Memory
451
views
answered
Jul 9, 2017
CO and Architecture
made-easy-test-series
co-and-architecture
cache-memory
multilevel-cache
bad-question
+
–
2
votes
187
Average Writing Time
Consider a two level memory hierarchy. L1(cache) has an accessing time of 10 ns and main memory has an accessing time of 20ns. Writing or updating contents into their memory takes 20 ns and 30 ns for L1 and main memory respectively. Assume L1 gives misses 80% of the time. The average writing time for system (in ns) if it uses write-through technique is _____________
Consider a two level memory hierarchy. L1(cache) has an accessing time of 10 ns and main memory has an accessing time of 20ns. Writing or updating contents into their me...
352
views
answered
Jul 9, 2017
1
votes
188
Difference between Memory Access and memory Reference ?
Difference between Memory Access and memory Reference ?
Difference between Memory Access and memory Reference ?
879
views
answered
Jul 9, 2017
3
votes
189
Difference between simultaneous and hierarchical memory access with formula? When to apply which one?
1.2k
views
answered
Jul 9, 2017
1
votes
190
Toc Peter Linz
can anyone provide solution of Toc Peter Linz 6th edition ?
can anyone provide solution of Toc Peter Linz 6th edition ?
1.6k
views
answered
Jul 9, 2017
Theory of Computation
theory-of-computation
peter-linz
+
–
Page:
« prev
1
2
3
4
5
6
7
8
9
10
11
...
20
next »
Email or Username
Show
Hide
Password
I forgot my password
Remember
Log in
Register