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1
votes
1
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 26
A block-set-associative cache consists of a total of $64$ blocks divided into $4$-block sets. The main memory contains $4096$ blocks (each consisting of $128$ words). Answer the following questions based on this info: How many bits are there in a main ... and $8,7,4$ $20$ and $6,7,8$ $19$ and $8,4,7$ $17$ and $8,7,4$
A block-set-associative cache consists of a total of $64$ blocks divided into $4$-block sets. The main memory contains $4096$ blocks (each consisting of $128$ words).Answ...
339
views
answered
Dec 1, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
cache-memory
+
–
1
votes
2
Test by Bikram | Computer Organization and Architecture | Test 1 | Question: 13
A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns. The speed-up rotation of the pipeline for $10$ tasks will be _______.
A non-pipeline system takes $25$ ns to process a task. The same task can be processed in a six-segment pipeline in a clock cycle of $10$ ns.The speed-up rotation of the p...
317
views
answered
Dec 1, 2016
CO and Architecture
tbb-coa-1
co-and-architecture
pipelining
speedup
numerical-answers
+
–
–1
votes
3
Test by Bikram | Data Structures | Test 2 | Question: 28
A circular linked list is used to represents a queue. A single variable L is used to access the queue. To which node should L point such that both the operation enqueue and dequeue can be performed in constant time ? node next to front front node not possible with a single node rear node
A circular linked list is used to represents a queue. A single variable L is used to access the queue. To which node should L point such that both the operation enqueue a...
772
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answered
Dec 1, 2016
Programming in C
tbb-ds-2
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–
2
votes
4
Test by Bikram | Digital Logic | Test 2 | Question: 22
Synchronous counters eliminate the delay problems encountered with asynchronous counters because: The input clock pulses are applied only to the first and last stages. The input clock pulses are applied only to the last stage. The ... used to activate any of the counter stages. The input clock pulses are applied simultaneously to each stage.
Synchronous counters eliminate the delay problems encountered with asynchronous counters because:The input clock pulses are applied only to the first and last stages.The ...
241
views
answered
Dec 1, 2016
Digital Logic
tbb-digital-logic-2
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–
2
votes
5
Test by Bikram | Digital Logic | Test 2 | Question: 21
On the fifth clock pulse, a $4$-bit Johnson sequence is $Q0 = 0, \ Q1 = 1, \ Q2 = 1$, and $Q3 = 1$. On the sixth clock pulse, the sequence is ________. $Q0 = 1, \ Q1 = 0, \ Q2 = 0, \ Q3 = 0$ $Q0 = 1, \ Q1 = 1, \ Q2 = 1, \ Q3 = 0$ $Q0 = 0, \ Q1 = 0, \ Q2 = 1, \ Q3 = 1$ $Q0 = 0, \ Q1 = 0, \ Q2 = 0, \ Q3 = 1$
On the fifth clock pulse, a $4$-bit Johnson sequence is $Q0 = 0, \ Q1 = 1, \ Q2 = 1$, and $Q3 = 1$. On the sixth clock pulse, the sequence is ________.$Q0 = 1, \ Q1 = 0, ...
865
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answered
Dec 1, 2016
Digital Logic
tbb-digital-logic-2
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–
3
votes
6
Test by Bikram | Digital Logic | Test 2 | Question: 5
The Boolean expression $ A \cdot B+ A \cdot B+ A \cdot B$ is equivalent to: $A + B$ $A \cdot B$ $A \oplus B$ $A \cdot B + A' B'$
The Boolean expression $ A \cdot B+ A \cdot B+ A \cdot B$ is equivalent to:$A + B$$A \cdot B$$A \oplus B$$A \cdot B + A' B'$
190
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answered
Dec 1, 2016
Digital Logic
tbb-digital-logic-2
+
–
0
votes
7
Perimeter
Find the sum of the perimeters of all the rectangles with integral sides whose area is 216 sq. units.
Find the sum of the perimeters of all the rectangles with integral sides whose area is 216 sq. units.
892
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answered
Nov 30, 2016
1
votes
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GATE CSE 2005 | Question: 79
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in the ... $2$ $3$ $4$ $5$
Consider the following data path of a $\text{CPU}.$The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including increm...
24.1k
views
answered
Oct 31, 2015
CO and Architecture
gatecse-2005
co-and-architecture
machine-instruction
data-path
normal
+
–
–5
votes
9
GATE CSE 2001 | Question: 1.7, ISRO2008-18
More than one word are put in one cache block to: exploit the temporal locality of reference in a program exploit the spatial locality of reference in a program reduce the miss penalty none of the above
More than one word are put in one cache block to:exploit the temporal locality of reference in a programexploit the spatial locality of reference in a programreduce the m...
16.9k
views
answered
Oct 9, 2015
CO and Architecture
gatecse-2001
co-and-architecture
easy
cache-memory
isro2008
+
–
0
votes
10
ISRO2009-69
The 'command' used to change contents of one database using the contents of another database by linking them on a common key field? Replace Join Change Update
The 'command' used to change contents of one database using the contents of another database by linking them on a common key field?ReplaceJoinChangeUpdate
4.5k
views
answered
Oct 8, 2015
Databases
isro2009
databases
bad-question
+
–
1
votes
11
Hopcroft Ullman - Automata Theory, which edition should I prefer?
I read reviews about the third edition(indian edition) of this book, where it is mentioned that 3rd edition contains a lot of errors and 2nd edition is less erroneous than the 3rd.Anybody using 3rd edition please tell ... errata available for 3rd indian edition? Whether 3rd edition is worth buying or I should look for 2nd edition?
I read reviews about the third edition(indian edition) of this book, where it is mentioned that 3rd edition contains a lot of errors and 2nd edition is less erroneous tha...
677
views
answered
Oct 8, 2015
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