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Questions by DebRC
2
votes
0
answers
1
Split Phase | Self-Doubt | COA
How is split phase implemented in the hardware? For common register access between two stages, how is one clock cycle (Giving half a clock cycle to each of the stages) enough to satisfy work for both stages? Any reference to standard resources will also help.
How is split phase implemented in the hardware?For common register access between two stages, how is one clock cycle (Giving half a clock cycle to each of the stages) eno...
468
views
asked
Dec 6, 2022
CO and Architecture
co-and-architecture
operand-forwarding
operating-system
self-doubt
split-phase
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–
3
votes
3
answers
2
Made Easy: Linear Algebra (MSQ)
Let $A$ be a $3$ x $3$ matrix with rank $2$. Then, $AX=0$ has The trivial solution $X=0$. One independent solution. Two independent solution. Three independent solution.
Let $A$ be a $3$ x $3$ matrix with rank $2$. Then, $AX=0$ hasThe trivial solution $X=0$.One independent solution.Two independent solution.Three independent solution.
1.1k
views
asked
Sep 19, 2022
Linear Algebra
linear-algebra
engineering-mathematics
rank-of-matrix
matrix
system-of-equations
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–
2
votes
0
answers
3
Operating System: Self Doubt - Memory Management
Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately reside in MM. (assuming there's no page fault). Let, TLB Hit Ratio = x TLB Access ... for TLB miss it will be (a+c+p). But if this is true, why can't we store Page Table in a Cache?
Considering a system with Single-Level page table, with a TLB to reduce the access time of pages. A cache is also provided with the main memory. All the pages ultimately ...
366
views
asked
Sep 14, 2022
Operating System
memory-management
operating-system
paging
cache-memory
self-doubt
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–
1
votes
1
answer
4
Made Easy Test Series 2021: Operating System
Consider the following segment: Note : Assume the count = count + 1; will execute in 3' different instructions. Where, m[count] refers to memory value of count variable. Preemption can occur while executing the above instructions. Each of the tally function has a separate ... 15 b) Min = 2, Maximum = 15 c) Min = 1, Maximum = 15 d) Min = 15, Maximum = 15
Consider the following segment:Note : Assume the count = count + 1; will execute in ‘3’ different instructions.Where, m[count] refers to memory value of count variabl...
1.0k
views
asked
Sep 12, 2022
Operating System
operating-system
made-easy-test-series
context-switch
process-synchronization
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–
2
votes
1
answer
5
Computer Networks: Wild Card
What is wild card host and mask? What is its significance?
What is wild card host and mask? What is its significance?
379
views
asked
Sep 6, 2022
Computer Networks
computer-networks
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–
1
votes
2
answers
6
Is a Serial Schedule always Recoverable?
Is only conflict serializable schedules are recoverable? Or both view as well as conflict serializable schedules are recoverable? I have been seeing different answers in different forum.
Is only conflict serializable schedules are recoverable?Or both view as well as conflict serializable schedules are recoverable?I have been seeing different answers in di...
1.9k
views
asked
Aug 16, 2022
Databases
databases
concurrency
transaction-and-concurrency
serializability
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1
votes
3
answers
7
Are all Irrecoverable/Non-Recoverable schedules cascading?
Suppose, T1: W(X), T2: R(X), T1: W(X), T2: Commit, T1: Abort Here we can see T2 is getting committed before T1 aborts, so it is clearly an Irrecoverable schedule but is it cascading?
Suppose,T1: W(X), T2: R(X), T1: W(X), T2: Commit, T1: AbortHere we can see T2 is getting committed before T1 aborts, so it is clearly an Irrecoverable schedule but is it ...
739
views
asked
Nov 2, 2021
Databases
databases
transaction-and-concurrency
data
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