Register
Filter

Answers by Dexter

2 votes
1
Doubt database
What is basic difference between mandatory attributes and multivalued attributes???
What is basic difference between mandatory attributes and multivalued attributes???
1 votes
3
Question
On a system with N CPU, what is the maximum number of processes that can be in running state ? A) N process B)Depend on the processes in ready state C) Can't say
On a system with N CPU, what is the maximum number of processes that can be in running state ?A) N processB)Depend on the processes in ready stateC) Can't say
1 votes
4
Regular expression
What is the regular expression for sigma = {0,1} where each string has odd 0's. Which one is correct? A) 1*0(1*01*01*)* B) 1*01*(1*01*01*)*
What is the regular expression for sigma = {0,1} where each string has odd 0's. Which one is correct?A) 1*0(1*01*01*)*B) 1*01*(1*01*01*)*
7 votes
5
Control Word
A computer has 170 different operations. Word size is 4 Bytes. one word instruction requires two address fields. One address for register and one address for memory. If there are 37 registers then the memory size is ____ (in KB).
A computer has 170 different operations. Word size is 4 Bytes. one word instruction requires two address fields. One address for register and one address for memory. If t...
0 votes
7
NPTEL
Return value of xchg instruction is_____________ 1. Old value 2. New value 3 . 1 if operation succeeds and 0 if operation fails 4. None of the above
Return value of xchg instruction is_____________1. Old value2. New value3 . 1 if operation succeeds and 0 if operation fails4. None of the above
0 votes
8
NPTEL
By using Intel hardware xchg instruction ensures that The critical section is deadlock free Solution is starvation free Process enters CS in FIFO order More than one process enters critical section at same time Which of the above statement is TRUE?
By using Intel hardware xchg instruction ensures thatThe critical section is deadlock freeSolution is starvation freeProcess enters CS in FIFO orderMore than one process ...
0 votes
9
NPTEL
State True/False Bakery algorithm ensures that no process is starved. 1. True 2. False
State True/False Bakery algorithm ensures that no process is starved.1. True2. False
3 votes
11
self doubt
If there are no attributes in common between two relations R and S then, what should be the result of (R natural join S)? 1) R x S 2) $\phi$ I think option 2 because of following definition from Korth:
If there are no attributes in common between two relations R and S then, what should be the result of (R natural join S)?1) R x S2) $\phi$I think option 2 because of foll...
0 votes
12
NPTEL-Internetwork Security-Week2-Quiz-2
Which cipher is commonly used in network-based symmetric cryptographic applications? (A) Linear cipher (B) Block cipher (C) Permutation cipher (D) Stream cipher
Which cipher is commonly used in network-based symmetric cryptographic applications? (A) Linear cipher (B) Block cipher (C) Permutation cipher (D) Stream cipher
0 votes
14
Subnet Mask
What is the size of subnet mask? No. of bits in subnet mask or No. of subnets possible
What is the size of subnet mask?No. of bits in subnet mask or No. of subnets possible
4 votes
18
E R model
why not b) option
why not b) option
3 votes
19
MICROPROCESSOR PROGR
how many times the loop will be executed LXI H,0106 H DCR L LOOP :DCX H NZ LOOP HLT a)105 times b) 261 times c) 0 times d) forever
how many times the loop will be executedLXI H,0106 HDCR L LOOP :DCX HNZ LOOPHLTa)105 times b) 261 times c) 0 times d) forever
3 votes
20
Threads
Since every thread can access every memory address within the process’ address space, one thread can read, write, or even wipe out another thread’s stack. I am not getting the above statement, stack is specific to a thread then how we can access other thread's stack through Process' address space?
Since every thread can access every memory address within the process’ address space, one thread can read, write, or even wipe out another thread’s stack.I am not get...
13 votes
22
GATE CSE 2002 | Question: 1.9
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while: $\overline{INTA}$ is active HOLD is active READY is inactive None of the above
A device employing INTR line for device interrupt puts the CALL instruction on the data bus while:$\overline{INTA}$ is activeHOLD is activeREADY is inactiveNone of the ab...
1 votes
23
CO 2001
A processor needs software interrupt to (a) test the interrupt system of the processor (b) implement co routines (c) obtain system services which need execution of priviledge instructions (d) return from subroutine
A processor needs software interrupt to(a) test the interrupt system of the processor(b) implement co routines(c) obtain system services which need execution of priviledg...
Page: