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1
answer
1
Pc relative mode addressing
What is the intial pc value meaning 530=Pc + value what should be the pc value 631 or 632 or 633 basically the instruction length is not give so how can i determine the addr loaded in pc hen instructtion at 630 is executing because if instruction length is 4 bytes it should be 634 thanks in advance
commented
Jan 10
in
CO and Architecture

1.4k
views
coandarchitecture
addressingmodes
1
answer
2
unitary matrix
A is a unitary matrix. Then eigen value of A are (a) 1, – 1 (b) 1, – i (c) i, – i (d) – 1, i
comment reshown
Dec 2, 2019
in
Linear Algebra

175
views
5
answers
3
GATE2016224
In an Ethernet local area network, which one of the following statements is TRUE? A station stops to sense the channel once it starts transmitting a frame. The purpose of the jamming signal is to pad the frames that are smaller than ... transmit the packet even after the collision is detected. The exponential back off mechanism reduces the probability of collision on retransmissions.
commented
Nov 21, 2019
in
Computer Networks

3.1k
views
gate20162
computernetworks
ethernet
normal
5
answers
4
GATE2006IT65
In the $4B/5B$ encoding scheme, every $4$ bits of data are encoded in a $5$bit codeword. It is required that the codewords have at most $1$ leading and at most $1$ trailing zero. How many are such codewords possible? $14$ $16$ $18$ $20$
answered
Nov 21, 2019
in
Computer Networks

3.4k
views
gate2006it
computernetworks
encoding
permutationandcombination
normal
9
answers
5
GATE2014325
Host A (on TCP/IP v4 network A) sends an IP datagram D to host B (also on TCP/IP v4 network B). Assume that no error occurred during the transmission of D. When D reaches B, which of the following IP header field(s) may be different from that of the original datagram D? TTL Checksum ... $\text{i}$ and $\text{ii}$ only $\text{ii}$ and $\text{iii}$ only $\text{i, ii}$ and $\text{iii}$
commented
Nov 20, 2019
in
Computer Networks

5.3k
views
gate20143
computernetworks
ippacket
normal
12
answers
6
GATE200447
Consider a system with a twolevel paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. The ... instruction execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$
answered
Nov 18, 2019
in
CO and Architecture

22.4k
views
gate2004
coandarchitecture
virtualmemory
normal
4
answers
7
GATE2016131
The size of the data count register of a $\text{DMA}$ controller is $16 \text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times the $\text{DMA}$ controller needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.
commented
Nov 16, 2019
in
CO and Architecture

5.6k
views
gate20161
coandarchitecture
dma
normal
numericalanswers
10
answers
8
GATE2016230
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement the computation $F(G(X_{i}))$ for $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.
commented
Nov 16, 2019
in
CO and Architecture

8.4k
views
gate20162
coandarchitecture
datapath
normal
numericalanswers
1
answer
9
Gate19871vi
Microprogrammed control unit: is faster than a hardwired control unit facilitates easy implementation of new instructions is useful when very small programs are to be run usually refers to control unit of a microprocessor
commented
Nov 16, 2019
in
CO and Architecture

2.4k
views
gate1987
microprogramming
controlunit
easy
coandarchitecture
6
answers
10
GATE200642
A CPU has a fivestage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new instructions ... is: $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$
commented
Nov 15, 2019
in
CO and Architecture

7k
views
gate2006
coandarchitecture
pipelining
normal
2
answers
11
GATE200112
Consider a $5$stage pipeline  IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle and all ... Show all data dependencies between the four instructions. Identify the data hazards. Can all hazards be avoided by forwarding in this case.
commented
Nov 15, 2019
in
CO and Architecture

4.2k
views
gate2001
coandarchitecture
pipelining
normal
descriptive
6
answers
12
GATE199311
In the threelevel memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$ ... such a page swap is $T_i$. Calculate the average time $t_A$ required for a processor to read one word from this memory system.
commented
Nov 15, 2019
in
CO and Architecture

3.2k
views
gate1993
coandarchitecture
cachememory
normal
1
answer
13
GATE200210
In a C program, an array is declared as $\text{float} \ A[2048]$. Each array element is $4 \ \text{Bytes}$ in size, and the starting address of the array is $0x00000000$. This program is run on a computer that has a direct mapped ... occur? Justify your answer briefly. Assume that the data cache is initially empty and that no other data or instruction accesses are to be considered.
commented
Nov 15, 2019
in
CO and Architecture

1.8k
views
gate2002
coandarchitecture
cachememory
normal
descriptive
1
answer
14
GATE2008IT33
Consider the following languages. $L_1 = \{a^i b^j c^k \mid i = j, k \geq 1\}$ $L_2 = \{a^i b^j \mid j = 2i, i \geq 0\}$ Which of the following is true? $L_1$ is not a CFL but $L_2$ is $L_1 \cap L_2 = \varnothing $ and $L_1$ is nonregular $L_1 \cup L_2$ is not a CFL but $L_2$ is There is a $4$state PDA that accepts $L_1$, but there is no DPDA that accepts $L_2$.
commented
Nov 11, 2019
in
Theory of Computation

1.5k
views
gate2008it
theoryofcomputation
normal
identifyclasslanguage
2
answers
15
TIFR2018B11
Consider the language $L\subseteq \left \{ a,b,c \right \}^{*}$ defined as $L = \left \{ a^{p}b^{q}c^{r} : p=q\quad or\quad q=r \quad or\quad r=p \right \}.$ Which of the following answer is TRUE about the complexity of this language? $L$ is regular ... $L,$ defined as $\overline{L} = \left \{ a,b,c \right \}^{*}\backslash L,$ is regular. $L$ is regular, contextfree and decidable
commented
Nov 11, 2019
in
Theory of Computation

533
views
tifr2018
identifyclasslanguage
theoryofcomputation
10
answers
16
GATE201835
Consider the following languages: $\{a^mb^nc^pd^q \mid m+p=n+q, \text{ where } m, n, p, q \geq 0 \}$ $\{a^mb^nc^pd^q \mid m=n \text{ and }p=q, \text{ where } m, n, p, q \geq 0 \}$ ... Which of the above languages are contextfree? I and IV only I and II only II and III only II and IV only
commented
Nov 11, 2019
in
Theory of Computation

5.4k
views
gate2018
theoryofcomputation
identifyclasslanguage
contextfreelanguages
normal
2
answers
17
TIFR2019B10
Let the language $D$ be defined in the binary alphabet $\{0,1\}$ as follows: $D:= \{ w \in \{0,1\}^* \mid \text{ substrings 01 and 10 occur an equal number of times in w} \}$ For example , $101 \in D$ while $1010 \notin D$. Which of the ... ? $D$ is regular $D$ is contextfree but not regular $D$ is decidable but not contextfree $D$ is decidable but not in NP $D$ is undecidable
answered
Nov 11, 2019
in
Theory of Computation

321
views
tifr2019
theoryofcomputation
identifyclasslanguage
2
answers
18
GATE20022.14
Which of the following is true? The complement of a recursive language is recursive The complement of a recursively enumerable language is recursively enumerable The complement of a recursive language is either recursive or recursively enumerable The complement of a contextfree language is contextfree
commented
Nov 11, 2019
in
Theory of Computation

1.7k
views
gate2002
theoryofcomputation
easy
closureproperty
5
answers
19
GATE200661
The atomic fetchandset $x, y$ instruction unconditionally sets the memory location $x$ to $1$ and fetches the old value of $x$ in $y$ without allowing any intervening access to the memory location $x$. Consider the following implementation of $P$ and $V$ ... set, a pair of normal load/store can be used The implementation of $V$ is wrong The code does not implement a binary semaphore
commented
Nov 6, 2019
in
Operating System

8.8k
views
gate2006
operatingsystem
processsynchronization
normal
4
answers
20
GATE20022.21
Which combination of the following features will suffice to characterize an OS as a multiprogrammed OS? More than one program may be loaded into main memory at the same time for execution If a program waits for certain events such as I/O, another program is immediately scheduled for ... program is immediately scheduled for execution. (a) (a) and (b) (a) and (c) (a), (b) and (c)
commented
Nov 6, 2019
in
Operating System

3.7k
views
gate2002
operatingsystem
normal
process
4
answers
21
GATE19973.9
Thrashing reduces page I/O decreases the degree of multiprogramming implies excessive page I/O improve the system performance
commented
Nov 5, 2019
in
Operating System

3.3k
views
gate1997
operatingsystem
pagereplacement
easy
3
answers
22
GATE19992.10
A multiuser, multiprocessing operating system cannot be implemented on hardware that does not support Address translation DMA for disk transfer At least two modes of CPU execution (privileged and nonprivileged) Demand paging
answered
Nov 5, 2019
in
Operating System

4.5k
views
gate1999
operatingsystem
normal
virtualmemory
4
answers
23
GATE19936.8
The details of an interrupt cycle are shown in figure. Given that an interrupt input arrives every $1$ msec, what is the percentage of the total time that the CPU devotes for the main program execution.
commented
Nov 4, 2019
in
Operating System

2k
views
gate1993
operatingsystem
interrupts
normal
2
answers
24
TIFR2018A14
Let $A$ be an $n\times n$ invertible matrix with real entries whose row sums are all equal to $c$. Consider the following statements: Every row in the matrix $2A$ sums to $2c$. Every row in the matrix $A^{2}$ sums to $c^{2}$. Every row in the matrix $A^{1}$ ... $(1)$ and $(2)$ are correct but not necessarily statement $(3)$ all the three statements $(1), (2),$ and $(3)$ are correct
commented
Oct 25, 2019
in
Linear Algebra

570
views
tifr2018
matrices
linearalgebra
4
answers
25
GATE200440
Suppose each set is represented as a linked list with elements in arbitrary order. Which of the operations among $\text{union, intersection, membership, cardinality}$ will be the slowest? $\text{union}$ only $\text{intersection, membership}$ $\text{membership, cardinality}$ $\text{union, intersection}$
commented
Oct 22, 2019
in
DS

4.3k
views
gate2004
datastructures
linkedlists
normal
5
answers
26
GATE2016234
A complete binary minheap is made by including each integer in $[1, 1023]$ exactly once. The depth of a node in the heap is the length of the path from the root of the heap to that node. Thus, the root is at depth $0$. The maximum depth at which integer $9$ can appear is _________.
commented
Oct 22, 2019
in
DS

7.1k
views
gate20162
datastructures
heap
normal
numericalanswers
5
answers
27
GATE2015143
The graph shown below has $8$ edges with distinct integer edge weights. The minimum spanning tree (MST) is of weight $36$ and contains the edges: $\{(A, C), (B, C), (B, E), (E, F), (D, F)\}$. The edge weights of only those edges which are in the MST are given in the figure shown below. The minimum possible sum of weights of all $8$ edges of this graph is_______________.
commented
Oct 21, 2019
in
Algorithms

6.2k
views
gate20151
algorithms
spanningtree
normal
numericalanswers
5
answers
28
GATE2016114
Let $G$ be a weighted connected undirected graph with distinct positive edge weights. If every edge weight is increased by the same value, then which of the following statements is/are TRUE? $P$: Minimum spanning tree of $G$ does not change. $Q$: Shortest path between any pair of vertices does not change. $P$ only $Q$ only Neither $P$ nor $Q$ Both $P$ and $Q$
commented
Oct 21, 2019
in
Algorithms

6.3k
views
gate20161
algorithms
spanningtree
normal
4
answers
29
GATE2015140
An algorithm performs $(\log N)^{\frac{1}{2}}$ find operations , $N$ insert operations, $(\log N)^{\frac{1}{2}}$ delete operations, and $(\log N)^{\frac{1}{2}}$ decreasekey operations on a set of data items with keys ... use, if the goal is to achieve the best total asymptotic complexity considering all the operations? Unsorted array Min  heap Sorted array Sorted doubly linked list
commented
Oct 19, 2019
in
Algorithms

7.8k
views
gate20151
algorithms
datastructures
normal
timecomplexity
8
answers
30
GATE200620, ISRO201517
Consider the following log sequence of two transactions on a bank account, with initial balance $12000,$ that transfer $2000$ to a mortgage payment and then apply a $5\%$ interest. T1 start T1 B old $=1200$ new $=10000$ ... records $2$ and $3$ because transaction T1 has committed We can apply redo and undo operations in arbitrary order because they are idempotent
commented
Oct 13, 2019
in
Databases

8.8k
views
gate2006
databases
transactions
normal
isro2015
3
answers
31
GATE201911
Consider the following two statements about database transaction schedules: Strict twophase locking protocol generates conflict serializable schedules that are also recoverable. Timestampordering concurrency control protocol with Thomas' Write Rule can generate view serializable schedules that are ... of the above statements is/are TRUE? I only II only Both I and II Neither I nor II
commented
Oct 9, 2019
in
Databases

3.1k
views
gate2019
databases
transactions
3
answers
32
GATE200657
Consider this C code to swap two integers and these five statements: the code void swap (int *px, int *py) { *px = *px  *py; *py = *px + *py; *px = *py  *px; } S1: will generate a compilation error S2: may generate a segmentation fault ... swap procedure correctly for some but not all valid input pointers S5: may add or subtract integers and pointers S1 S2 and S3 S2 and S4 S2 and S5
commented
Oct 5, 2019
in
Programming

5.5k
views
gate2006
programming
programminginc
normal
1
answer
33
Peter Linz Edition 4 Exercise 7.3 Question 3 (Page No. 200)
Is the language $L =$ {$a^nb^n : n ≥ 1$} $∪$ {$b$} deterministic?
commented
Sep 23, 2019
in
Theory of Computation

22
views
peterlinz
theoryofcomputation
contextfreelanguages
1
answer
34
TANCET 2017 DBMS
commented
Sep 20, 2019
in
Databases

38
views
tancet
6
answers
35
GATE2005IT42
Two concurrent processes $P1$ and $P2$ use four shared resources $R1, R2, R3$ and $R4$, as shown below. $\begin{array}{ll}\hline \textbf{P1} & \textbf{P2} \\ \text{Compute: } & \text{Compute;} \\ \text{Use $ ... If only binary semaphores are used to enforce the above scheduling constraints, what is the minimum number of binary semaphores needed? $1$ $2$ $3$ $4$
answered
Sep 18, 2019
in
Operating System

3.9k
views
gate2005it
operatingsystem
processsynchronization
normal
3
answers
36
GATE200218b
The functionality of atomic TESTANDSET assembly language instruction is given by the following C function int TESTANDSET (int *x) { int y; A1: y=*x; A2: *x=1; A3: return y; } Complete the following C functions for implementing code for ... starvationfree? For the above solution, show by an example that mutual exclusion is not ensured if TESTANDSET instruction is not atomic?
commented
Sep 18, 2019
in
Operating System

617
views
gate2002
operatingsystem
processsynchronization
normal
descriptive
7
answers
37
GATE20001.21
Let $m[0]\ldots m[4]$ be mutexes (binary semaphores) and $P[0]\ldots P[4]$ be processes. Suppose each process $P[i]$ executes the following: wait (m[i]; wait (m(i+1) mod 4]); ........... release (m[i]); release (m(i+1) mod 4]); This could cause Thrashing Deadlock Starvation, but not deadlock None of the above
commented
Sep 18, 2019
in
Operating System

4.9k
views
gate2000
operatingsystem
processsynchronization
normal
13
answers
38
Minimum number of tables to represent ERDiagram
How many minimum relations required for given ER diagram ?
commented
Sep 15, 2019
in
Databases

1.7k
views
erdiagram
databases
ertorelational
relational
3
answers
39
GATE2014231
Consider the procedure below for the ProducerConsumer problem which uses semaphores: semaphore n = 0; semaphore s = 1; void producer() { while(true) { produce(); semWait(s); addToBuffer(); semSignal(s); semSignal(n); } } void consumer() { while(true) { semWait ... s when the buffer is empty. The starting value for the semaphore $n$ must be $1$ and not $0$ for deadlockfree operation.
commented
Sep 12, 2019
in
Operating System

4.1k
views
gate20142
operatingsystem
processsynchronization
normal
2
answers
40
GATE199620
Consider the syntaxdirected translation schema (SDTS) shown below: $E\rightarrow E + E$ {print “+”} $E\rightarrow E * E$ {print “.”} $E\rightarrow id$ {print id.name} $E\rightarrow (E)$ An LRparser executes ... the corresponding production. Draw the parse tree and write the translation for the sentence. $(a+b)*(c+d)$, using SDTS given above.
commented
Sep 2, 2019
in
Compiler Design

953
views
gate1996
compilerdesign
syntaxdirectedtranslation
normal
50,737
questions
57,385
answers
198,560
comments
105,386
users