Recent activity by Doraemon / GATE Overflow for GATE CSE

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GATE Overflow Test Series | Theory of Computation | Test 1 | Question: 12
The regular expression for the language of all strings over $\Sigma = \{a,b\}$ with no consecutive $a's$ or $b's$ is given by _____ (Mark all the appropriate choices) $(\varepsilon + b)(ab)^{\ast}(\varepsilon + a)$ ... $a(ba)^{\ast} + a(ba)^{\ast} b + (ba)^{\ast} + (ba)^{\ast}b$

The regular expression for the language of all strings over $\Sigma = \{a,b\}$ with no consecutive $a's$ or $b's$ is given by _____ (Mark all the appropriate choices)$(\v...

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commented Nov 11, 2020

2 answers

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GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 11
A computer using expanding opcode technique has $32-bit$ instructions and $13-bit$ addresses. If there are $60$ two-address instructions, and $128$ zero-address instructions, approximately how many one-address instructions can it support? $32\;K$ $20\;K$ $64\;K$ $16\;K$

A computer using expanding opcode technique has $32-bit$ instructions and $13-bit$ addresses. If there are $60$ two-address instructions, and $128$ zero-address instructi...

371 views

commented Nov 7, 2020

1 answer

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GATE Overflow Test Series | Computer Organization and Architecture | Test 1 | Question: 30
Consider a CPU with an average CPI of $1.4$ ... allocate policy with the probability of a cache block being dirty being $0.15$ (round off to $2$ decimal places).

Consider a CPU with an average CPI of $1.4$ when all memory accesses hit on the cache.Assume an instruction mix$$\begin{array}{|c | c|}\hline\text{ALU }& 45\%\\\text{LOAD...

825 views

commented Nov 7, 2020

3 answers

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GATE CSE 2006 | Question: 62, ISRO2016-50
A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table entries and is $4$-way set associative. The minimum size of the TLB tag is: $\text{11 bits}$ $\text{13 bits}$ $\text{15 bits}$ $\text{20 bits}$

A CPU generates $32$-bit virtual addresses. The page size is $4$ KB. The processor has a translation look-aside buffer (TLB) which can hold a total of $128$ page table en...

25.8k views

commented Sep 16, 2020

4 answers

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GATE CSE 2004 | Question: 20
Which of the following addressing modes are suitable for program relocation at run time? Absolute addressing Based addressing Relative addressing Indirect addressing I and IV I and II II and III I, II and IV

Which of the following addressing modes are suitable for program relocation at run time?Absolute addressingBased addressingRelative addressingIndirect addressingI and IVI...

12.1k views

answered Jun 2, 2020

9 answers

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GATE CSE 2018 | Question: 35
Consider the following languages: $\{a^mb^nc^pd^q \mid m+p=n+q, \text{ where } m, n, p, q \geq 0 \}$ $\{a^mb^nc^pd^q \mid m=n \text{ and }p=q, \text{ where } m, n, p, q \geq 0 \}$ ... Which of the above languages are context-free? I and IV only I and II only II and III only II and IV only

Consider the following languages:$\{a^mb^nc^pd^q \mid m+p=n+q, \text{ where } m, n, p, q \geq 0 \}$$\{a^mb^nc^pd^q \mid m=n \text{ and }p=q, \text{ where } m, n, p, q \ge...

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comment edited May 20, 2020

1 answer

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Michael Sipser Edition 3 Exercise 2 Question 9 (Page No. 155)
Give a context-free grammar that generates the language $A=\{a^{i}b^{j}c^{k}\mid i=j$ $\text{or}$ $ j=k$ $\text{where}$ $ i,j,k\geq 0\}.$ Is your grammar ambiguous$?$ Why or why not$?$

Give a context-free grammar that generates the language $A=\{a^{i}b^{j}c^{k}\mid i=j$ $\text{or}$ $ j=k$ $\text{where}$ $ i,j,k\geq 0\}.$ Is your grammar ambiguous$?$ Why...

555 views

commented May 20, 2020

6 answers

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GATE CSE 2011 | Question: 15
The minimum number of $\text{D}$ flip-flops needed to design a mod-258 counter is 9 8 512 258

The minimum number of $\text{D}$ flip-flops needed to design a mod-258 counter is98512258

15.0k views

commented May 10, 2020

1 answer

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GATE CSE 1994 | Question: 2-1
The number of flip-flops required to construct a binary modulo $N$ counter is __________

The number of flip-flops required to construct a binary modulo $N$ counter is __________

6.3k views

commented May 10, 2020

2 answers

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GATE CSE 2001 | Question: 11
A sequential circuit takes an input stream of $0's$ and $1's$ and produces an output stream of $0's$ and $1's.$ Initially it replicates the input on its output until two consecutive $0's$ are encountered on the input. From then ... Give the minimized sum-of-product expression for $\text{J}$ and $\text{K}$ inputs of one of its state flip-flops

A sequential circuit takes an input stream of $0's$ and $1's$ and produces an output stream of $0's$ and $1's.$ Initially it replicates the input on its output until two ...

5.2k views

commented May 10, 2020

3 answers

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TIFR CSE 2010 | Part B | Question: 21
For $x \in \{0,1\}$, let $\lnot x$ denote the negation of $x$, that is $\lnot \, x = \begin{cases}1 & \mbox{iff } x = 0\\ 0 & \mbox{iff } x = 1\end{cases}$. If $x \in \{0,1\}^n$, then $\lnot \, x$ denotes the component wise negation of $x$; that ... $g(x) = f(x) \land f(\lnot x)$ $g(x) = f(x) \lor f(\lnot x)$ $g(x) = \lnot f(\lnot x)$ None of the above.

For $x \in \{0,1\}$, let $\lnot x$ denote the negation of $x$, that is $$\lnot \, x = \begin{cases}1 & \mbox{iff } x = 0\\ 0 & \mbox{iff } x = 1\end{cases}$$.If $x \in \...

3.4k views

commented May 8, 2020

1 answer

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From Geeksforgeeks
Given A, an array of size n, comprised of an increasing sequence of numbers followed immediately by a decreasing one. What is worst case time complexity of optimal algorithm to determine if a given number x is in the array?

Given A, an array of size n, comprised of an increasing sequence of numbers followed immediately by a decreasing one. What is worst case time complexity of optimal algori...

2.4k views

commented May 3, 2020

1 answer

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Kenneth Rosen Edition 6th Exercise 1.5 Question 10 (Page No. 73)
For each of theses sets of premises, what relevant conclusions can be drawn? (b)"If I work, it is either sunny or partly sunny." "I worked last Monday or I worked Last Friday." "It was not ... only eat what tastes good." "You do not eat Tofu." "Cheeseburgers are not healthy to eat."

For each of theses sets of premises, what relevant conclusions can be drawn?(b)"If I work, it is either sunny or partly sunny." "I worked last Monday or I worked Last Fri...

2.5k views

commented Apr 10, 2020

4 answers

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GATE CSE 2000 | Question: 2.26
In SQL, relations can contain null values, and comparisons with null values are treated as unknown. Suppose all comparisons with a null value are treated as false. Which of the following pairs is not equivalent? $x = 5 \quad not (not (x = 5))$ $x = 5 \quad x > 4$ and $x < 6,$ where $x$ is an integer $x ≠ 5 \quad not (x = 5)$ none of the above

In SQL, relations can contain null values, and comparisons with null values are treated as unknown. Suppose all comparisons with a null value are treated as false. Which ...

18.8k views

commented Apr 8, 2020

13 answers

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Minimum number of tables to represent ER-Diagram
How many minimum relations required for given ER diagram ?

How many minimum relations required for given ER diagram ?

8.8k views

commented Apr 6, 2020

2 answers

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ACE Academy: Recognition of CFG
$L1 =\left \{ a^{m} b^{n} c^{p} | \left ( m \geq n \right )\text{or} \left ( n = p \right ) \right \}$ $L2 =\left \{ a^{m} b^{n} c^{p} | \left ( m \geq n \right )\text{and} \left ( n = p \right ) \right \}$ $(a)$ Both are NCFL’s $(b)$ L1 is DCFL and L2 is NCFL $(c)$ L1 is NCFL and L2 is not context-free $(d)$ Both are not context-free

$L1 =\left \{ a^{m} b^{n} c^{p} | \left ( m \geq n \right )\text{or} \left ( n = p \right ) \right \}$ $L2 =\left \{ a^{m} b^{n} c^{p} | \left ( m \geq n \right )\text{a...

795 views

commented Mar 31, 2020

1 answer

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Pc relative mode addressing
What is the intial pc value meaning 530=Pc + value what should be the pc value 631 or 632 or 633 basically the instruction length is not give so how can i determine the addr loaded in pc hen instructtion at 630 is executing because if instruction length is 4 bytes it should be 634 thanks in advance

What is the intial pc value meaning 530=Pc + value what should be the pc value 631 or 632 or 633 basically the instruction length is not give so how can i determine the a...

5.2k views

commented Jan 10, 2020

1 answer

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unitary matrix
A is a unitary matrix. Then eigen value of A are (a) 1, – 1 (b) 1, – i (c) i, – i (d) – 1, i

A is a unitary matrix. Then eigen value of A are(a) 1, – 1 (b) 1, – i(c) i, – i (d) – 1, i

15.3k views

comment reshown Dec 2, 2019

7 answers

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GATE CSE 2016 Set 2 | Question: 24
In an Ethernet local area network, which one of the following statements is TRUE? A station stops to sense the channel once it starts transmitting a frame. The purpose of the jamming signal is to pad the frames that are ... the packet even after the collision is detected. The exponential back off mechanism reduces the probability of collision on retransmissions.

In an Ethernet local area network, which one of the following statements is TRUE?A station stops to sense the channel once it starts transmitting a frame.The purpose of t...

11.2k views

commented Nov 21, 2019

6 answers

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GATE IT 2006 | Question: 65
In the $\text{4B/5B}$ encoding scheme, every $4$ bits of data are encoded in a $5$-bit codeword. It is required that the codewords have at most $1$ leading and at most $1$ trailing zero. How many are such codewords possible? $14$ $16$ $18$ $20$

In the $\text{4B/5B}$ encoding scheme, every $4$ bits of data are encoded in a $5$-bit codeword. It is required that the codewords have at most $1$ leading and at most $1...

10.1k views

answered Nov 21, 2019

9 answers

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GATE CSE 2014 Set 3 | Question: 25
Host A (on TCP/IP v4 network A) sends an IP datagram D to host B (also on TCP/IP v4 network B). Assume that no error occurred during the transmission of D. When D reaches B, which of the following IP header field(s) may be different from that of the original datagram ... $\text{ii}$ only $\text{ii}$ and $\text{iii}$ only $\text{i, ii}$ and $\text{iii}$

Host A (on TCP/IP v4 network A) sends an IP datagram D to host B (also on TCP/IP v4 network B). Assume that no error occurred during the transmission of D. When D reaches...

16.5k views

commented Nov 20, 2019

19 answers

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GATE CSE 2004 | Question: 47
Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An average instruction takes $100$ nanoseconds of CPU time, and two memory accesses. ... execution time? $\text{645 nanoseconds}$ $\text{1050 nanoseconds}$ $\text{1215 nanoseconds}$ $\text{1230 nanoseconds}$

Consider a system with a two-level paging scheme in which a regular memory access takes $150$ $nanoseconds$, and servicing a page fault takes $8$ $milliseconds$. An avera...

63.7k views

answered Nov 17, 2019

6 answers

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GATE CSE 2016 Set 1 | Question: 31
The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times ... needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.

The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memo...

18.6k views

commented Nov 16, 2019

12 answers

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GATE CSE 2016 Set 2 | Question: 30
Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two instances of $U_{G}$, it is required to implement ... $1 \leq i \leq 10$. Ignoring all other delays, the minimum time required to complete this computation is ____________ nanoseconds.

Suppose the functions $F$ and $G$ can be computed in $5$ and $3$ nanoseconds by functional units $U_{F}$ and $U_{G}$, respectively. Given two instances of $U_{F}$ and two...

22.6k views

commented Nov 16, 2019

2 answers

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GATE CSE 1987 | Question: 1-vi
A microprogrammed control unit Is faster than a hard-wired control unit. Facilitates easy implementation of new instruction. Is useful when very small programs are to be run. Usually refers to the control unit of a microprocessor.

A microprogrammed control unitIs faster than a hard-wired control unit.Facilitates easy implementation of new instruction.Is useful when very small programs are to be run...

7.4k views

commented Nov 16, 2019

9 answers

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GATE CSE 2006 | Question: 42
A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the target address and evaluates the condition in the third stage of the pipeline. The processor stops fetching new ... : $\text{1.0 second}$ $\text{1.2 seconds}$ $\text{1.4 seconds}$ $\text{1.6 seconds}$

A CPU has a five-stage pipeline and runs at $1$ GHz frequency. Instruction fetch happens in the first stage of the pipeline. A conditional branch instruction computes the...

21.2k views

commented Nov 15, 2019

2 answers

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GATE CSE 2001 | Question: 12
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle ... Show all data dependencies between the four instructions. Identify the data hazards. Can all hazards be avoided by forwarding in this case.

Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or registe...

18.0k views

commented Nov 15, 2019

6 answers

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GATE CSE 1993 | Question: 11
In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$ ... a page swap is $T_i$. Calculate the average time $t_A$ required for a processor to read one word from this memory system.

In the three-level memory hierarchy shown in the following table, $p_i$ denotes the probability that an access request will refer to $M_i$.$$\begin{array}{|c|c|c|c|} \hli...

11.0k views

commented Nov 15, 2019

1 answer

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GATE CSE 2002 | Question: 10
In a C program, an array is declared as $\text{float} \ A[2048]$. Each array element is $4 \ \text{Bytes}$ in size, and the starting address of the array is $0x00000000$. This program is run on a computer that has a direct ... ? Justify your answer briefly. Assume that the data cache is initially empty and that no other data or instruction accesses are to be considered.

In a C program, an array is declared as $\text{float} \ A[2048]$. Each array element is $4 \ \text{Bytes}$ in size, and the starting address of the array is $0x00000000$....

6.2k views

commented Nov 15, 2019

2 answers

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GATE IT 2008 | Question: 33
Consider the following languages. $L_1 = \{a^i b^j c^k \mid i = j, k \geq 1\}$ $L_2 = \{a^i b^j \mid j = 2i, i \geq 0\}$ Which of the following is true? $L_1$ is not a CFL but $L_2$ is $L_1 \cap L_2 = \varnothing $ and $L_1$ is non-regular $L_1 \cup L_2$ is not a CFL but $L_2$ is There is a $4$-state PDA that accepts $L_1$, but there is no DPDA that accepts $L_2$.

Consider the following languages.$L_1 = \{a^i b^j c^k \mid i = j, k \geq 1\}$$L_2 = \{a^i b^j \mid j = 2i, i \geq 0\}$Which of the following is true?$L_1$ is not a CFL bu...

6.0k views

commented Nov 11, 2019

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