# Recent activity by Gaurangi Katiyar

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Let a relation R with n tuples occupying X blocks and relation S with m tuples occupying Y blocks. 5 blocks of main memory are allocated to store records of R and S to perform join. What will be the access cost of a) R join S b) S join R
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What will be the value of z at the end of the following program? int value(int *x) { static int count; while(*x) { count = count + (*x & 1); *x>> =1; } return count; } main( ) { int a[ ]={3,5,6,4}; int y = 0 ,z = 0; for(; y < sizeof(a)/sizeof(int) ; y++) { z = a[y] + value( &a[y]); } }
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Consider Shubhani wants to transfer a file from host A to host B connected via a link with 100 Mbps bandwidth. Shubhani chooses maximum file size to transfer with MSS of 1460 B. If total 66 bytes of transport, network and data link layer header are added to each segment before the packet is sent over the link, then the time to transmit the file is _____s.
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Consider a file consist 30,000 fixed length record.Block size 1024 bytes,record size 100 bytes.Search key 9 bytes, block pointer size 6 bytes. A) How many levels of index required if 1st level uses dense index. B) How many levels of index required if 1st level uses sparse index.
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Consider A lives in Delhi, connected to the internet via a 100 Mbps connection retrieve a 250 KB webpage from server in Chennai where page contain 3 images of 500 KB each. Assume one way propagation delay is 75ms and A's access link is the bandwidth bottleneck for this ... to appear on A's screen using nonpersistent Http and T2 is time using persistent Http then,what are the values of T1 and T2?
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Consider two machines, A and B, connected by a 100 Mbps Ethernet with three store and forward relay switches in path between them. Suppose that no other machines are using the Ethernet, that each link introduces a propagation delay 12 microsecond, and that switch being ... transfer time for a 1500 bytes packet, as measured from transmission of first bit from A to receipt of last bit at B?
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The matrices $\begin{bmatrix} \cos\theta && -\sin\theta \\ \sin\theta && \cos\theta \end{bmatrix}$ and $\begin{bmatrix} a && 0\\ 0&& b \end{bmatrix}$ commute under multiplication if $a=b \text{ or } \theta = n\pi, n$ an integer always never if $a \cos\theta = b \sin\theta$
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suppose there are 4 sorted lists of n/4 elements each. if we merge these list into a single sorted list of n elements, for the n=400 number of key comparisons in the worst case using an efficient algorithm is
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Consider a 5 stage pipeline which allows overlapping of all instructions except branch instructions.The target of branch instructions is not available until the branch instruction is completed. Let each stage delay is 20 ns and there are 30% branch instructions. What is performance gain of pipeline over non pipeline
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Consider 2 pipeline with the following specification Stall cycle for memory pipeline no. Of stage memory 1 A k single port 0 B k dual port The pipeline allows all instructions except memory based instructions. If 2 memory operations can not be done in same clock. The penalty is 1 clock. Let there are 20% memory instructions obtain Sa/Sb A. 0.833     b.  0.53      c.  0.94     d. 0.24
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How to calculate how many memory references will Instruction Decode phase take in an Instruction Cycle?
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What is the difference between concatenation of two linked lists and union of two linked lists?
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What will be the output of following program if we use a) static scoping b) dynamic scoping? int a= 1,b=2; main( ) { int a=20,b=30; Print(a,b); C( ); Print(a,b); D( ); } C( ) { int a= 50; print (a,b); D( ); Print(a,b); } D( ) { Print (a,b); a=3; b=4; Print(a,b); F( ); } F( ) { int b =6; Print( a,b); a=7; b=8; }
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The ALU, the bus and all the registers in the data path are of identical size. All operations including incrementation of the PC and the GPRs are to be carried out in the ALU. Two clock cycles are needed for memory read operation - the first one for loading address in the ... 1; PC <= M[R0]; The minimum number of CPU clock cycles needed during the execution cycle of this instruction is: 2 3 4 5
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Suppose that in 1000 memory references thee are 40 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from L2 cache to memory is 100 cycle.The hit time of L2 is 10 cycle. The hit time of L1 is 1 clock cycle. What is the average memory access time?
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suppose that in 1000 memory reference there are 40 misses in the first level cache and 20 misses in the second level cache. Assume miss penalty from the L2 cache to memory is 100 cycles the hit time of the L2 cache is 10 clock cycles.the hit time of the L1 cache is ... = (memory reference per instruction) x (miss rate) x (miss penalty) right?? so which miss rate and miss penalty should i put here?
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Suppose the random variable X has the probability distribution given below: X -2 -1 0 1 2 P(X=X) 0.25 0.20 0.15 0.35 0.05 Let $Y=(2*(X^2))+6$.The expected value E(Y) is: A) 9.5 B) 6. C )15.5. D )18