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Recent activity by Gupta731
7
answers
1
GATE CSE 2010 | Question: 28
The degree sequence of a simple graph is the sequence of the degrees of the nodes in the graph in decreasing order. Which of the following sequences can not be the degree sequence of any graph? $7, 6, 5, 4, 4, 3, 2, 1$ $6, 6, 6, 6, 3, 3, 2, 2$ $7, 6, 6, 4, 4, 3, 2, 2$ $8, 7, 7, 6, 4, 2, 1, 1$ I and II III and IV IV only II and IV
The degree sequence of a simple graph is the sequence of the degrees of the nodes in the graph in decreasing order. Which of the following sequences can not be the degree...
18.5k
views
commented
Oct 22, 2020
Graph Theory
gatecse-2010
graph-theory
degree-of-graph
+
–
1
answer
2
GATE CSE 2015 Set 3 | Question: 45
If for non-zero $x, \: af(x) + bf(\frac{1}{x}) = \frac{1}{x} - 25$ where $a \neq b \text{ then } \int\limits_1^2 f(x)dx$ is $\frac{1}{a^2 - b^2} \begin{bmatrix} a(\ln 2 - 25) + \frac{47b}{2} \end{bmatrix}$ ... $\frac{1}{a^2 - b^2} \begin{bmatrix} a(\ln 2 - 25) - \frac{47b}{2} \end{bmatrix}$
If for non-zero $x, \: af(x) + bf(\frac{1}{x}) = \frac{1}{x} - 25$ where $a \neq b \text{ then } \int\limits_1^2 f(x)dx$ is$\frac{1}{a^2 - b^2} \begin{bmatrix} a(\ln 2 - ...
8.1k
views
commented
Sep 29, 2020
Calculus
gatecse-2015-set3
calculus
integration
normal
+
–
7
answers
3
GATE CSE 2011 | Question: 31
Given $i = \sqrt{-1}$, what will be the evaluation of the definite integral $\int \limits_0^{\pi/2} \dfrac{\cos x +i \sin x} {\cos x - i \sin x} dx$ ? $0$ $2$ $-i$ $i$
Given $i = \sqrt{-1}$, what will be the evaluation of the definite integral $\int \limits_0^{\pi/2} \dfrac{\cos x +i \sin x} {\cos x - i \sin x} dx$ ?$0$$2$$-i$$i$
10.9k
views
commented
Sep 29, 2020
Calculus
gatecse-2011
calculus
integration
normal
+
–
6
answers
4
GATE CSE 2003 | Question: 79
A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical addresses are both $32$ bits wide. The memory is byte addressable. For virtual to physical address translation, ... tables of this process is $\text{8 KB}$ $\text{12 KB}$ $\text{16 KB}$ $\text{20 KB}$
A processor uses $\text{2-level}$ page tables for virtual to physical address translation. Page tables for both levels are stored in the main memory. Virtual and physical...
23.9k
views
answered
Sep 27, 2020
Operating System
gatecse-2003
operating-system
normal
virtual-memory
+
–
1
answer
5
Test by Bikram | Databases | Test 2 | Question: 11
Relation $L( p,q)$ is stored in $100$ blocks, with $50$ records per block (or tuples) of $L$ fitting in one block. Relation $K(m,n)$ is stored in $200$ blocks with $100$ ... $K$. Therefore, the total number of blocks required in the result of join operation is: ______ blocks.
Relation $L( p,q)$ is stored in $100$ blocks, with $50$ records per block (or tuples) of $L$ fitting in one block. Relation $K(m,n)$ is stored in $200$ blocks with $100$ ...
641
views
commented
Sep 21, 2020
Databases
tbb-dbms-2
numerical-answers
databases
joins
+
–
2
answers
6
Test by Bikram | Databases | Test 1 | Question: 23
Given R(A,B,C,D,E) with the set of FDs, F{AB→CD, ABC → E, C → A} the normal form of R is 2NF BCNF 4NF 3NF
Given R(A,B,C,D,E) with the set of FDs,F{AB→CD, ABC → E, C → A}the normal form of R is2NFBCNF4NF3NF
534
views
commented
Sep 20, 2020
Databases
tbb-dbms-1
+
–
2
answers
7
Test by Bikram | Databases | Test 1 | Question: 3
Suppose that the transaction T1 and T2 access the same database items. ... these two transactions? Dirty Read will occur Lost update will occur Both T1 and T2 are serial schedule This is an example of uncommitted data problem
Suppose that the transaction T1 and T2 access the same database items.$$\begin{array}{|l|l|} \hline T1 & T2 \\ \hline \text{read(X)} & {} \\ X=X-N & {} \\ \hline {} & \te...
508
views
commented
Sep 20, 2020
Databases
tbb-dbms-1
+
–
6
answers
8
GATE CSE 2013 | Question: 3
Which one of the following does NOT equal $\begin{vmatrix} 1 & x & x^{2}\\ 1& y & y^{2}\\ 1 & z & z^{2} \end{vmatrix} \quad ?$ $\begin{vmatrix} 1& x(x+1)& x+1\\ 1& y(y+1) & y+1\\ 1& z(z+1) & z+1 \end{vmatrix}$ ...
Which one of the following does NOT equal $$\begin{vmatrix} 1 & x & x^{2}\\ 1& y & y^{2}\\ 1 & z & z^{2} \end{vmatrix} \quad ?$$$\begin{vmatrix} 1& x(x+1)& x+1\\ 1& y(y+1...
9.3k
views
commented
Sep 18, 2020
Linear Algebra
gatecse-2013
linear-algebra
normal
determinant
+
–
7
answers
9
GATE CSE 1993 | Question: 01.1
The eigen vector $(s)$ of the matrix $\begin{bmatrix} 0 &0 &\alpha\\ 0 &0 &0\\ 0 &0 &0 \end{bmatrix},\alpha \neq 0$ is (are) $(0,0,\alpha)$ $(\alpha,0,0)$ $(0,0,1)$ $(0,\alpha,0)$
The eigen vector $(s)$ of the matrix $$\begin{bmatrix} 0 &0 &\alpha\\ 0 &0 &0\\ 0 &0 &0 \end{bmatrix},\alpha \neq 0$$ is (are)$(0,0,\alpha)$$(\alpha,0,0)$$(0,0,1)$$(0,\al...
11.6k
views
answer edited
Sep 18, 2020
Linear Algebra
gate1993
eigen-value
linear-algebra
easy
multiple-selects
+
–
10
answers
10
GATE CSE 2003 | Question: 18
In a bottom-up evaluation of a syntax directed definition, inherited attributes can always be evaluated be evaluated only if the definition is L-attributed be evaluated only if the definition has synthesized attributes never be evaluated
In a bottom-up evaluation of a syntax directed definition, inherited attributes canalways be evaluatedbe evaluated only if the definition is L-attributedbe evaluated only...
37.0k
views
commented
Sep 9, 2020
Compiler Design
gatecse-2003
compiler-design
syntax-directed-translation
normal
+
–
4
answers
11
GATE CSE 2012 | Question: 36
Consider the program given below, in a block-structured pseudo-language with lexical scoping and nesting of procedures permitted. Program main; Var ... Procedure A1; Var ... Call A2; End A1 Procedure A2; Var ... Procedure A21; Var ... Call ... The correct set of activation records along with their access links is given by:
Consider the program given below, in a block-structured pseudo-language with lexical scoping and nesting of procedures permitted.Program main; Var ... Procedure A1; Var ....
13.0k
views
commented
Sep 9, 2020
Compiler Design
gatecse-2012
compiler-design
runtime-environment
normal
+
–
2
answers
12
Gateforum Test Series: CO & Architecture - Microprogramming
826
views
answer selected
Sep 6, 2020
CO and Architecture
gateforum-test-series
co-and-architecture
microprogramming
+
–
2
answers
13
GATE CSE 1988 | Question: 2ix
What is the type of the language $L$, where $L=\{a^n b^n \mid 0 < n < 327 \text{-th prime number} \}$
What is the type of the language $L$, where $L=\{a^n b^n \mid 0 < n < 327 \text{-th prime number} \}$
3.0k
views
commented
Aug 31, 2020
Theory of Computation
gate1988
normal
descriptive
theory-of-computation
identify-class-language
+
–
2
answers
14
GATE CSE 1987 | Question: 2m
State whether the following statements are TRUE or FALSE: The problem as to whether a Turing machine $M$ accepts input $w$ is undecidable.
State whether the following statements are TRUE or FALSE:The problem as to whether a Turing machine $M$ accepts input $w$ is undecidable.
3.9k
views
commented
Aug 31, 2020
Theory of Computation
gate1987
theory-of-computation
turing-machine
decidability
true-false
+
–
2
answers
15
GATE CSE 1990 | Question: 15a
Is the language generated by the grammar $G$ regular? If so, give a regular expression for it, else prove otherwise G: $S \rightarrow aB$ $B \rightarrow bC$ $C \rightarrow xB$ $C \rightarrow c$
Is the language generated by the grammar $G$ regular? If so, give a regular expression for it, else prove otherwiseG: $S \rightarrow aB$$B \rightarrow bC$$C \rightarro...
3.2k
views
commented
Aug 28, 2020
Theory of Computation
gate1990
descriptive
theory-of-computation
regular-language
regular-grammar
+
–
4
answers
16
GATE CSE 1999 | Question: 2.22
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typically has fewer instructions has fewer addressing modes has more registers is easier to implement using hard-wired logic
The main difference(s) between a CISC and a RISC processor is/are that a RISC processor typicallyhas fewer instructionshas fewer addressing modeshas more registersis easi...
9.0k
views
commented
Aug 19, 2020
CO and Architecture
gate1999
co-and-architecture
normal
cisc-risc-architecture
multiple-selects
+
–
3
answers
17
GATE CSE 1999 | Question: 1.22
The main memory of a computer has $2\;\text{cm}$ blocks while the cache has $2\;\text{c}$ blocks. If the cache uses the set associative mapping scheme with $2$ blocks per set, then block $k$ of the main memory maps to the set: $(k \mod m)$ of the cache $(k \mod c)$ of the cache $(k \mod 2c)$ of the cache $(k \mod 2\; cm)$ of the cache
The main memory of a computer has $2\;\text{cm}$ blocks while the cache has $2\;\text{c}$ blocks. If the cache uses the set associative mapping scheme with $2$ blocks per...
7.7k
views
commented
Aug 18, 2020
CO and Architecture
gate1999
co-and-architecture
cache-memory
normal
+
–
10
answers
18
GATE CSE 2007 | Question: 80
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in the system. A $50 \times 50$ two-dimensional array of bytes is stored in the main ... data cache do not change in between the two accesses. How many data misses will occur in total? $48$ $50$ $56$ $59$
Consider a machine with a byte addressable main memory of $2^{16}$ bytes. Assume that a direct mapped data cache consisting of $32$ lines of $64$ bytes each is used in th...
32.5k
views
comment edited
Aug 18, 2020
CO and Architecture
gatecse-2007
co-and-architecture
cache-memory
normal
+
–
9
answers
19
GATE CSE 2006 | Question: 80
A CPU has a $32 KB$ direct mapped cache with $128$ byte-block size. Suppose A is two dimensional array of size $512 \times512$ with elements that occupy $8$-bytes each. Consider the following two C code segments, $P1$ and $P2$. P1: for (i=0; i<512; i++) { for (j=0; ... $P1$ be $M_{1}$and that for $P2$ be $M_{2}$. The value of $M_{1}$ is: $0$ $2048$ $16384$ $262144$
A CPU has a $32 KB$ direct mapped cache with $128$ byte-block size. Suppose A is two dimensional array of size $512 \times512$ with elements that occupy $8$-bytes each. C...
16.8k
views
commented
Aug 18, 2020
CO and Architecture
gatecse-2006
co-and-architecture
cache-memory
normal
+
–
2
answers
20
GATE CSE 2001 | Question: 9
A CPU has $32-bit$ memory address and a $256 \ KB$ cache memory. The cache is organized as a $4-way$ set associative cache with cache block size of $16$ bytes. What is the number of sets in the cache? What is the size (in bits) of ... are required to find the byte offset within a cache block? What is the total amount of extra memory (in bytes) required for the tag bits?
A CPU has $32-bit$ memory address and a $256 \ KB$ cache memory. The cache is organized as a $4-way$ set associative cache with cache block size of $16$ bytes.What is the...
13.1k
views
comment edited
Aug 18, 2020
CO and Architecture
gatecse-2001
co-and-architecture
cache-memory
normal
descriptive
+
–
5
answers
21
GATE CSE 1998 | Question: 18
For a set-associative Cache organization, the parameters are as follows: ... $1 \leq m \leq l$. Give the value of the hit ratio for $l = 1$.
For a set-associative Cache organization, the parameters are as follows:$$\begin{array}{|c|l|} \hline \text {$t _c$} & \text{Cache Access Time }\\\hline \text{$t _m$} &...
12.9k
views
comment edited
Aug 18, 2020
CO and Architecture
gate1998
co-and-architecture
cache-memory
descriptive
+
–
5
answers
22
GATE CSE 1996 | Question: 26
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: ... of less than $100 nsec$? What is the average access time achieved using the chosen sizes of level $1$ and level $2$ memories?
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below:$$\overset{ \text {Level $1$ (Cache memory)} \\ \text{Access time = ...
15.1k
views
comment edited
Aug 17, 2020
CO and Architecture
gate1996
co-and-architecture
cache-memory
normal
+
–
5
answers
23
GATE CSE 2019 | Question: 8
Consider $Z=X-Y$ where $X, Y$ and Z are all in sign-magnitude form. X and Y are each represented in $n$ bits. To avoid overflow, the representation of $Z$ would require a minimum of: $n$ bits $n-1$ bits $n+1$ bits $n+2$ bits
Consider $Z=X-Y$ where $X, Y$ and Z are all in sign-magnitude form. X and Y are each represented in $n$ bits. To avoid overflow, the representation of $Z$ would require a...
13.6k
views
commented
Aug 14, 2020
Digital Logic
gatecse-2019
digital-logic
number-representation
1-mark
+
–
4
answers
24
GATE CSE 2016 Set 2 | Question: 09
Let $X$ be the number of distinct $16$-bit integers in $2's$ complement representation. Let $Y$ be the number of distinct $16$-bit integers in sign magnitude representation Then $X - Y$ is______.
Let $X$ be the number of distinct $16$-bit integers in $2's$ complement representation. Let $Y$ be the number of distinct $16$-bit integers in sign magnitude representati...
12.3k
views
commented
Aug 14, 2020
Digital Logic
gatecse-2016-set2
digital-logic
number-representation
normal
numerical-answers
+
–
5
answers
25
GATE CSE 2004 | Question: 66
Let $A = 1111 1010$ and $B = 0000 1010$ be two $8-bit$ $2’s$ complement numbers. Their product in $2’s$ complement is $1100 0100$ $1001 1100$ $1010 0101$ $1101 0101$
Let $A = 1111 1010$ and $B = 0000 1010$ be two $8-bit$ $2’s$ complement numbers. Their product in $2’s$ complement is$1100 0100$$1001 1100$$1010 0101$$1101 0101$
19.1k
views
comment edited
Aug 13, 2020
Digital Logic
gatecse-2004
digital-logic
number-representation
easy
+
–
1
answer
26
GATE CSE 1997 | Question: 71
Let $f=(\bar{w} + y)(\bar{x} +y)(w+\bar{x}+z)(\bar{w}+z)(\bar{x}+z)$ Express $f$ as the minimal sum of products. Write only the answer. If the output line is stuck at $0$, for how many input combinations will the value of $f$ be correct?
Let $f=(\bar{w} + y)(\bar{x} +y)(w+\bar{x}+z)(\bar{w}+z)(\bar{x}+z)$Express $f$ as the minimal sum of products. Write only the answer.If the output line is stuck at $0$, ...
3.2k
views
commented
Aug 11, 2020
Digital Logic
gate1997
digital-logic
min-sum-of-products-form
numerical-answers
+
–
1
answer
27
GATE CSE 2002 | Question: 8
Consider the following circuit. $A = a_2a_1a_0$ and $B=b_2b_1b_0$ are three bit binary numbers input to the circuit. The output is $Z=z_3z_2z_1z_0$. R0, R1 and R2 are registers with loading clock shown. The registers are loaded with their input data with the falling ... b. What does the circuit implement?
Consider the following circuit. $A = a_2a_1a_0$ and $B=b_2b_1b_0$ are three bit binary numbers input to the circuit. The output is $Z=z_3z_2z_1z_0$. R0, R1 and R2 are reg...
3.1k
views
commented
Aug 9, 2020
Digital Logic
gatecse-2002
digital-logic
normal
descriptive
digital-counter
+
–
6
answers
28
GATE CSE 2006 | Question: 36
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ ...
Given two three bit numbers $a_{2}a_{1}a_{0}$ and $b_{2}b_{1}b_{0}$ and $c$ the carry in, the function that represents the carry generate function when these two numbers ...
15.1k
views
commented
Aug 6, 2020
Digital Logic
gatecse-2006
digital-logic
normal
carry-generator
adder
+
–
7
answers
29
GATE CSE 2006 | Question: 40
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray code of $ (n+1)(modulo 16)$ ... $ g_{3}(h_{3}h_{2}h_{1}h_{0})=\sum (0,1,6,7,10,11,12,13) $
Consider numbers represented in 4-bit Gray code. Let $ h_{3}h_{2}h_{1}h_{0}$ be the Gray code representation of a number $n$ and let $ g_{3}g_{2}g_{1}g_{0}$ be the Gray...
20.5k
views
commented
Aug 4, 2020
Digital Logic
gatecse-2006
digital-logic
number-representation
binary-codes
normal
+
–
1
answer
30
Morris Mano Edition 3 Exercise 1 Question 12 (Page No. 33)
Noting that $3 ^2 = 9$, Formulate a simple procedure for converting base-3 numbers to base-9 directly.use the procedure to convert the $(2110201102220) _3$ to base-9.
Noting that $3 ^2 = 9$, Formulate a simple procedure for converting base-3 numbers to base-9 directly.use the procedure to convert the $(2110201102220) _3$ to base-9.
3.8k
views
answer edited
Aug 3, 2020
Digital Logic
number-representation
digital-logic
morris-mano
+
–
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