Recent activity by JAINchiNMay / GATE Overflow for GATE CSE

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GATE CSE 2003 | Question: 83
A $2$ $km$ long broadcast LAN has $10^7$ bps bandwidth and uses CSMA/CD. The signal travels along the wire at $2 \times 10^8$ m/s. What is the minimum packet size that can be used on this network? $50$ $\text{bytes}$ $100$ $\text{bytes}$ $200$ $\text{bytes}$ None of the above

A $2$ $km$ long broadcast LAN has $10^7$ bps bandwidth and uses CSMA/CD. The signal travels along the wire at $2 \times 10^8$ m/s. What is the minimum packet size that ca...

13.8k views

commented May 4, 2023

0 answers

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We reached the station late, and _______ missed the train.

538 views

closed Feb 16, 2023

2 answers

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GATE CSE 2023 | GA Question: 4
A survey for a certain year found that $90\%$ of pregnant women received medical care at least once before giving birth. Of these women, $60\%$ received medical care from doctors, while $40\%$ received medical care from other healthcare providers. ... at most once from a doctor. Less than half of the pregnant women received medical care at most once from a doctor.

A survey for a certain year found that $90\%$ of pregnant women received medical care at least once before giving birth. Of these women, $60\%$ received medical care from...

6.5k views

commented Feb 15, 2023

6 answers

4

GATE CSE 2022 | Question: 52
Consider the queues $Q_{1}$ containing four elements and $Q_{2}$ containing none (shown as the $\textsf{Initial State}$ in the figure). The only operations allowed on these two queues are $\textsf{Enqueue (Q, element)}$ ... $\textsf{Final State}$ in the figure) without using any additional storage is________________.

Consider the queues $Q_{1}$ containing four elements and $Q_{2}$ containing none (shown as the $\textsf{Initial State}$ in the figure). The only operations allowed on the...

18.7k views

commented Feb 1, 2023

3 answers

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GATE CSE 2022 | Question: 53
Consider two files systems $\text{A}$ and $\text{B}$, that use contiguous allocation and linked allocation, respectively. A file of size $100$ blocks is already stored in $\text{A}$ and also in $\text{B}$. Now, consider inserting a new block in the middle of ... $\text{B}$ are $n_{A}$ and $n_{B}$, respectively, then the value of $n_{A} + n_{B}$ is__________________.

Consider two files systems $\text{A}$ and $\text{B}$, that use contiguous allocation and linked allocation, respectively. A file of size $100$ blocks is already stored in...

9.8k views

comment edited Feb 1, 2023

2 answers

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GATE CSE 2022 | GA Question: 8
A box contains five balls of same size and shape. Three of them are green coloured balls and two of them are orange coloured balls. Balls are drawn from the box one at a time. If a green ball is drawn, it is not replaced. If an orange ball is drawn, it is replaced with ... an orange ball in the next draw? $\frac{1}{2}$ $\frac{8}{25}$ $\frac{19}{50}$ $\frac{23}{50}$

A box contains five balls of same size and shape. Three of them are green coloured balls and two of them are orange coloured balls. Balls are drawn from the box one at a ...

9.9k views

commented Feb 1, 2023

7 answers

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GATE CSE 2019 | Question: 9
Let $X$ be a square matrix. Consider the following two statements on $X$. $X$ is invertible Determinant of $X$ is non-zero Which one of the following is TRUE? I implies II; II does not imply I II implies I; I does not imply II I does not imply II; II does not imply I I and II are equivalent statements

Let $X$ be a square matrix. Consider the following two statements on $X$.$X$ is invertibleDeterminant of $X$ is non-zeroWhich one of the following is TRUE?I implies II; I...

10.7k views

answer edited Jan 29, 2023

6 answers

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GATE CSE 1997 | Question: 12
Consider a hash table with $n$ buckets, where external (overflow) chaining is used to resolve collisions. The hash function is such that the probability that a key value is hashed to a particular bucket is $\frac{1}{n}$. The hash table is initially ... in any of the $K$ insertions? What is the probability that the first collision occurs at the $K^{th}$ insertion?

Consider a hash table with $n$ buckets, where external (overflow) chaining is used to resolve collisions. The hash function is such that the probability that a key value ...

10.6k views

comment edited Jan 28, 2023

7 answers

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GATE CSE 1990 | Question: 7-b
In a two-level virtual memory, the memory access time for main memory, $t_{M}=10^{-8}$ sec, and the memory access time for the secondary memory, $t_D=10^{-3}$ sec. What must be the hit ratio, $H$ such that the access efficiency is within $80$ percent of its maximum value?

In a two-level virtual memory, the memory access time for main memory, $t_{M}=10^{-8}$ sec, and the memory access time for the secondary memory, $t_D=10^{-3}$ sec. What m...

19.4k views

commented Jan 27, 2023

2 answers

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self_doubt
what is page fault service time ? what are its factor and how it is related/not related with the memory access time?? plss help with suitable example

what is page fault service time ? what are its factor and how it is related/not related with the memory access time??plss help with suitable example

769 views

answer edited Jan 27, 2023

6 answers

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GATE IT 2006 | Question: 51
Which one of the choices given below would be printed when the following program is executed? #include <stdio.h> int a1[] = {6, 7, 8, 18, 34, 67}; int a2[] = {23, 56, 28, 29}; int a3[] = {-12, 27, -31}; int *x[] = {a1, a2, a3}; void print(int *a[]) { printf("%d," ... (x); } $8, -12, 7, 23, 8$ $8, 8, 7, 23, 7$ $-12, -12, 27, -31, 23$ $-12, -12, 27, -31, 56$

Which one of the choices given below would be printed when the following program is executed? #include <stdio.h int a1[] = {6, 7, 8, 18, 34, 67}; int a2[] = {23, 5...

13.0k views

commented Jan 25, 2023

6 answers

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GATE CSE 2016 Set 2 | Question: 22
Suppose a database schedule $S$ involves transactions $T_1,\ldots,T_n$ . Construct the precedence graph of $S$ with vertices representing the transactions and edges representing the conflicts. If $S$ is serializable, which one of ... to yield a serial schedule? Topological order Depth-first order Breadth-first order Ascending order of the transaction indices

Suppose a database schedule $S$ involves transactions $T_1,\ldots,T_n$ . Construct the precedence graph of $S$ with vertices representing the transactions and edges repr...

13.3k views

commented Jan 24, 2023

4 answers

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GATE CSE 2015 Set 2 | Question: 1
Consider the following transaction involving two bank accounts $x$ and $y$. read(x); x:=x-50; write (x); read(y); y:=y+50; write(y) The constraint that the sum of the accounts $x$ and $y$ should remain constant is that of Atomicity Consistency Isolation Durability

Consider the following transaction involving two bank accounts $x$ and $y$.read(x); x:=x-50; write (x); read(y); y:=y+50; write(y)The constraint that the sum of the accou...

14.9k views

commented Jan 24, 2023

3 answers

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GATE CSE 2014 Set 1 | Question: 29
Consider the following four schedules due to three transactions (indicated by the subscript) using read and write on a data item x, denoted by $r(x)$ and $w(x)$ respectively. Which one of them is conflict serializable? $r_1(x)$; $r_2(x)$; $w_1(x)$; $r_3(x)$; $w_2(x)$; $r_2(x)$; ... $r_1(x)$; $w_2(x)$; $w_1(x)$; $r_2(x)$; $w_2(x)$; $r_3(x)$; $r_1(x)$; $w_1(x)$;

Consider the following four schedules due to three transactions (indicated by the subscript) using read and write on a data item x, denoted by $r(x)$ and $w(x)$ respectiv...

8.7k views

commented Jan 24, 2023

5 answers

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GATE CSE 2003 | Question: 29, ISRO2009-73
Which of the following scenarios may lead to an irrecoverable error in a database system? A transaction writes a data item after it is read by an uncommitted transaction A transaction reads a data item after it is read by an ... it is written by a committed transaction A transaction reads a data item after it is written by an uncommitted transaction

Which of the following scenarios may lead to an irrecoverable error in a database system?A transaction writes a data item after it is read by an uncommitted transactionA ...

14.9k views

answer edited Jan 24, 2023

14 answers

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GATE CSE 2008 | Question: 67
A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level page table is used for virtual to physical address translation, where the virtual address is used as ... tables are respectively $\text{20,20,20}$ $\text{24,24,24}$ $\text{24,24,20}$ $\text{25,25,24}$

A processor uses $36$ bit physical address and $32$ bit virtual addresses, with a page frame size of $4$ Kbytes. Each page table entry is of size $4$ bytes. A three level...

76.8k views

comment edited Jan 23, 2023

4 answers

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GATE CSE 2009 | Question: 34
A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address because It reduces the memory access time to read or write a memory location. It helps to reduce the size of ... is required by the translation lookaside buffer. It helps to reduce the number of page faults in page replacement algorithms.

A multilevel page table is preferred in comparison to a single level page table for translating virtual address to physical address becauseIt reduces the memory access ti...

14.6k views

answer edited Jan 23, 2023

5 answers

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GATE CSE 2016 Set 1 | Question: 20
Consider an arbitrary set of CPU-bound processes with unequal CPU burst lengths submitted at the same time to a computer system. Which one of the following process scheduling algorithms would minimize the average waiting time in the ... quantum less than the shortest CPU burst Uniform random Highest priority first with priority proportional to CPU burst length

Consider an arbitrary set of CPU-bound processes with unequal CPU burst lengths submitted at the same time to a computer system. Which one of the following process schedu...

14.3k views

commented Jan 23, 2023

4 answers

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GATE CSE 2016 Set 1 | Question: 52
Consider that $B$ wants to send a message $m$ that is digitally signed to $A$. Let the pair of private and public keys for $A$ and $B$ be denoted by ${K_{x}}^-$ and ${K_{x}}^+$ for $x=A, B$, respectively. Let $K_{x}(m)$ represent the operation of encrypting $m$ with a ... $\left\{m, {K_{A}}^-(H(m))\right\}$ $\left\{m, {K_{A}}^+(m)\right\}$

Consider that $B$ wants to send a message $m$ that is digitally signed to $A$. Let the pair of private and public keys for $A$ and $B$ be denoted by ${K_{x}}^-$ and ${K_{...

8.6k views

commented Jan 22, 2023

21 answers

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GATE CSE 2016 Set 1 | Question: 54
For a host machine that uses the token bucket algorithm for congestion control, the token bucket has a capacity of $1$ $\text{megabyte}$ and the maximum output rate is $20$ $\text{megabytes}$ per $\text{second}$. Tokens arrive at a rate to ... to send $12$ $\text{megabytes}$ of data. The minimum time required to transmit the data is _____________ $\text{seconds}$.

For a host machine that uses the token bucket algorithm for congestion control, the token bucket has a capacity of $1$ $\text{megabyte}$ and the maximum output rate is $2...

42.8k views

commented Jan 22, 2023

3 answers

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GATE CSE 2010 | Question: 33
A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID, OF and WO stages take $1$ clock cycle each for any instruction. The PO stage takes $1$ clock cycle for ... $13$ $15$ $17$ $19$

A $5-$stage pipelined processor has Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Perform Operation (PO) and Write Operand (WO) stages. The IF, ID,...

22.2k views

comment edited Jan 22, 2023

3 answers

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GATE CSE 2008 | Question: 76
Delayed branching can help in the handling of control hazards For all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or false, The instruction following the conditional branch instruction in memory is ... The first instruction in the taken path is executed The branch takes longer to execute than any other instruction

Delayed branching can help in the handling of control hazardsFor all delayed conditional branch instructions, irrespective of whether the condition evaluates to true or f...

18.0k views

comment edited Jan 22, 2023

10 answers

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GATE CSE 2009 | Question: 28
Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ ... the number of cycles needed to execute the following loop? For (i=1 to 2) {I1; I2; I3; I4;} $16$ $23$ $28$ $30$

Consider a $4$ stage pipeline processor. The number of cycles needed by the four instructions $I1, I2, I3, I4$ in stages $S1, S2, S3, S4$ is shown below:$$\begin{array}{|...

34.7k views

comment edited Jan 21, 2023

5 answers

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GATE CSE 2011 | Question: 21
Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a $32\text{-bit}$ ... mode implemented by this instruction for the operand in memory? Immediate addressing Register addressing Register Indirect Scaled Addressing Base Indexed Addressing

Consider a hypothetical processor with an instruction of type $\text{LW R1, 20(R2)}$, which during execution reads a $32\text{-bit}$ word from memory and stores it in a ...

17.6k views

comment edited Jan 21, 2023

10 answers

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GATE CSE 2013 | Question: 29
Consider a hard disk with $16$ recording surfaces $(0-15)$ having $16384$ cylinders $(0-16383)$ and each cylinder contains $64$ sectors $(0-63)$. Data storage capacity in each sector is $512$ bytes. Data are organized cylinder-wise and the addressing ... cylinder number of the last sector of the file, if it is stored in a contiguous manner? $1281$ $1282$ $1283$ $1284$

Consider a hard disk with $16$ recording surfaces $(0-15)$ having $16384$ cylinders $(0-16383)$ and each cylinder contains $64$ sectors $(0-63)$. Data storage capacity in...

30.3k views

commented Jan 21, 2023

5 answers

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GATE CSE 2009 | Question: 51
A hard disk has $63$ sectors per track, $10$ platters each with $2$ recording surfaces and $1000$ cylinders. The address of a sector is given as a triple $\langle c, h, s \rangle$, where $c$ is the cylinder number, $h$ is the surface number ... $\langle 400, 16, 29 \rangle$ corresponds to sector number: $505035$ $505036$ $505037$ $505038$

A hard disk has $63$ sectors per track, $10$ platters each with $2$ recording surfaces and $1000$ cylinders. The address of a sector is given as a triple $\langle c, h, s...

19.8k views

commented Jan 21, 2023

6 answers

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GATE CSE 2016 Set 1 | Question: 31
The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memory. The memory is byte addressable. The minimum number of times ... needs to get the control of the system bus from the processor to transfer the file from the disk to main memory is _________.

The size of the data count register of a $\text{DMA}$ controller is $16\;\text{bits}$. The processor needs to transfer a file of $29,154$ kilobytes from disk to main memo...

18.7k views

commented Jan 21, 2023

5 answers

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GATE CSE 2013 | Question: 28
Consider the following sequence of micro-operations. MBR ← PC MAR ← X PC ← Y Memory ← MBR Which one of the following is a possible operation performed by this sequence? Instruction fetch Operand fetch Conditional branch Initiation of interrupt service

Consider the following sequence of micro-operations.MBR ← PC MAR ← X PC ← Y Memory ← MBRWhich one of the following is a possible operation performed by this seque...

15.2k views

commented Jan 20, 2023

3 answers

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GATE CSE 1987 | Question: 4a
Find out the width of the control memory of a horizontal microprogrammed control unit, given the following specifications: $16$ control lines for the processor consisting of ALU and $7$ registers. Conditional branching facility by checking $4$ status bits. Provision to hold $128$ words in the control memory.

Find out the width of the control memory of a horizontal microprogrammed control unit, given the following specifications:$16$ control lines for the processor consisting ...

5.8k views

comment edited Jan 20, 2023

2 answers

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GATE CSE 2002 | Question: 2.7
Horizontal microprogramming: does not require use of signal decoders results in larger sized microinstructions than vertical microprogramming uses one bit for each control signal all of the above

Horizontal microprogramming:does not require use of signal decodersresults in larger sized microinstructions than vertical microprogramminguses one bit for each control ...

5.1k views

answer edited Jan 20, 2023

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