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Recent activity by Jevi
7
answers
1
GATE CSE 2017 Set 2 | Question: 1
The representation of the value of a $16\text{-bit}$ unsigned integer $X$ in hexadecimal number system is $\textsf{BCA9}$. The representation of the value of $X$ in octal number system is $571244$ $736251$ $571247$ $136251$
The representation of the value of a $16\text{-bit}$ unsigned integer $X$ in hexadecimal number system is $\textsf{BCA9}$. The representation of the value of $X$ in octal...
6.8k
views
answered
Feb 14, 2017
Digital Logic
gatecse-2017-set2
digital-logic
number-representation
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5
answers
2
GATE CSE 2017 Set 2 | Question: 05
Match the following according to input (from the left column) to the compiler phase (in the right column) that processes it: ... $\text{P-iii; Q-iv; R-i; S-ii}$ $\text{P-i; Q-iv; R-ii; S-iii}$
Match the following according to input (from the left column) to the compiler phase (in the right column) that processes it:$$\begin{array}{|l|l|}\hline \text{P. Syntax t...
9.6k
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answered
Feb 14, 2017
Compiler Design
gatecse-2017-set2
compiler-design
match-the-following
compilation-phases
easy
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4
answers
3
MadeEasy Test Series: Operating System - Process Schedule
Consider a uni-processor system executing four tasks T1, T2, T3, T4 each of which is composed of 10 sequence of jobs which arrive periodically at interval of 2, 4, 8, 16 ms resp. The priority of each task is directly ... Given all tasks initially arrive at t=0, the 2nd instance of T3 completes its execution at the end of ______ ms.
Consider a uni-processor system executing four tasks T1, T2, T3, T4 each of which is composed of 10 sequence of jobs which arrive periodically at interval of 2, 4, 8, 16 ...
1.0k
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answered
Dec 19, 2016
Operating System
made-easy-test-series
operating-system
process-scheduling
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2
answers
4
Test by Bikram | Compiler Design | Test 1 | Question: 30
Consider the following grammar: $S \rightarrow L = P \mid P$ $L \rightarrow ^*P \mid id$ $P \rightarrow L$ The above grammar is: Ambiguous SLR(1) LALR(1) None of the above
Consider the following grammar:$S \rightarrow L = P \mid P$$L \rightarrow ^*P \mid id$$P \rightarrow L$The above grammar is:AmbiguousSLR(1)LALR(1)None of the above
694
views
answered
Dec 14, 2016
Compiler Design
tbb-cd-1
compiler-design
grammar
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2
answers
5
How to Calculate the Lead and Last ? A very big doubt please clear
I have only heard about FIRST and FOLLOW . How to Calculate LEAD and LAST and TRAILING ..?
I have only heard about FIRST and FOLLOW .How to Calculate LEAD and LAST and TRAILING ..?
761
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answered
Dec 9, 2016
Compiler Design
compiler-design
parsing
first-and-follow
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2
answers
6
ME - CD
971
views
answered
Dec 5, 2016
Compiler Design
gate2017
compiler-design
parsing
made-easy-test-series
numerical-answers
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–
5
answers
7
ISRO2011-38
A fast wide SCSI-II disk drive spins at 7200 RPM, has a sector size of 512 bytes, and holds 160 sectors per track. Estimate the sustained transfer rate of this drive 576000 Kilobytes / sec 9600 Kilobytes / sec 4800 Kilobytes / sec 19200 Kilobytes / sec
A fast wide SCSI-II disk drive spins at 7200 RPM, has a sector size of 512 bytes, and holds 160 sectors per track. Estimate the sustained transfer rate of this drive57600...
4.7k
views
answered
Jun 19, 2016
Operating System
isro2011
operating-system
disk
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0
answers
8
PhD Admission
I have my GATE Score of 405 and I want to apply for PhD. I have B.E aggregate of 67% and Mtech of 8.6 CGPA and two years of IT experience in development. Can anyone suggest which colleges I should apply for PhD? Does having GRE Score of 300 has any advantage?
I have my GATE Score of 405 and I want to apply for PhD. I have B.E aggregate of 67% and Mtech of 8.6 CGPA and two years of IT experience in development. Can anyone sugge...
458
views
asked
Mar 23, 2016
2
answers
9
GATE CS set1 2016 answer key based on chat discussions
189 views GATE CS Set-1 Answer key based on chat discussions for CS section: 1. best cpu scheduling algo - srtf 2. no.of jk flipflops for a counter - 1 3. min no.of temporary registers - 6 4. worst case time complexities of mergesort, insertion, ... of Min Weight Spanning Tree of 6 distinct edges 1,2,3,4,5,6 - 7 52. missing while loop .. b!=a
189 viewsGATE CS Set-1 Answer key based on chat discussions for CS section:1. best cpu scheduling algo - srtf2. no.of jk flipflops for a counter - 13. min no.of temporary...
2.8k
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commented
Feb 11, 2016
1
answer
10
cs set1 questions
1. best cpu scheduling algo - srtf 2. no.of jk flipflops for a counter - 3 3. min no.of temporary registers ? 4. worst case time complexities of mergesort, insertion, quick 5. which does not convert one form of address to another - dhcp 6. 2's complement of ... from DBMS - UVWX or something right ? ok 51.Max value of Min Weight Spanning Tree of 6 distinct edges 1,2,3,4,5,6
1. best cpu scheduling algo - srtf2. no.of jk flipflops for a counter - 33. min no.of temporary registers ?4. worst case time complexities of mergesort, insertion, quick5...
1.2k
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commented
Feb 10, 2016
3
answers
11
English Terminology
Do we reduce PCP problem to our problem X to show that X is undecidable OR we reduce the problem X to PCP to show X's undecidability ?. A question has confused me in the terminology.
Do we reduce PCP problem to our problem X to show that X is undecidable OR we reduce the problem X to PCP to show X's undecidability ?. A question has confused me in the...
645
views
answered
Jan 4, 2016
Theory of Computation
theory-of-computation
decidability
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1
answer
12
Operating System
The question I answered was 4096 bytes and what the test answered is in KB and both the answers are correct . But in GATE how do we come to know whether the answer should be given in bytes or Kb or MB or GB?
The question I answered was 4096 bytes and what the test answered is in KB and both the answers are correct . But in GATE how do we come to know whether the answer should...
306
views
asked
Jan 2, 2016
Operating System
paging
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1
answer
13
Pipeline
Consider a 5 stage pipeline with IF, ID, EX, MEM and WB latencies 8, 6, 4, 6 and 4 respectively (in ns). If IF stage is made 50% faster, the percentage it will improve the performance CPU is __________.
Consider a 5 stage pipeline with IF, ID, EX, MEM and WB latencies 8, 6, 4, 6 and 4 respectively (in ns). If IF stage is made 50% faster, the percentage it will improve th...
3.0k
views
commented
Dec 29, 2015
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