Answers by Mohitdas / GATE Overflow for GATE CSE

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1

GATE CSE 2021 Set 2 | GA Question: 3
If $\theta$ is the angle, in degrees, between the longest diagonal of the cube and any one of the edges of the cube, then, $\cos \theta =$ $\frac{1}{2} \\$ $\frac{1}{\sqrt{3}} \\$ $\frac{1}{\sqrt{2}} \\$ $\frac{\sqrt{3}}{2}$

If $\theta$ is the angle, in degrees, between the longest diagonal of the cube and any one of the edges of the cube, then, $\cos \theta =$$\frac{1}{2} \\$$\frac{1}{\sqrt{...

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answered Jan 5, 2022

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2

NIELIT 2016 DEC Scientist B (IT) - Section B: 28
What is the possible number of reflexive relation on a set of $5$ elements? $2^{10}$ $2^{15}$ $2^{20}$ $2^{25}$

What is the possible number of reflexive relation on a set of $5$ elements?$2^{10}$$2^{15}$$2^{20}$$2^{25}$

534 views

answered Dec 18, 2021

0 votes

3

GATE IT 2005 | Question: 31
Let $f$ be a function from a set $A$ to a set $B$, $g$ a function from $B$ to $C$, and $h$ a function from $A$ to $C$, such that $h(a) = g(f(a))$ for all $a ∈ A.$ Which of the following statements is always true for all such functions $f$ and $g$? ... is onto $h$ is onto $\implies$ $f$ is onto $h$ is onto $\implies$ $g$ is onto $h$ is onto $\implies$ $f$ and $g$ are onto

Let $f$ be a function from a set $A$ to a set $B$, $g$ a function from $B$ to $C$, and $h$ a function from $A$ to $C$, such that $h(a) = g(f(a))$ for all $a ∈ A.$ Which...

8.9k views

answered Dec 10, 2021

2 votes

4

GATE IT 2006 | Question: 23
Let $P$, $Q$ and $R$ be sets let Δ denote the symmetric difference operator defined as $PΔQ=(P \cup Q) - (P ∩ Q).$ Using Venn diagrams, determine which of the following is/are TRUE? $PΔ (Q ∩ R) = (P Δ Q) ∩ (P Δ R)$ $P ∩ (Q ∩ R) = (P ∩ Q) Δ (P Δ R)$ I only II only Neither I nor II Both I and II

Let $P$, $Q$ and $R$ be sets let Δ denote the symmetric difference operator defined as $PΔQ=(P \cup Q) - (P ∩ Q).$ Using Venn diagrams, determine which of the followi...

5.8k views

answered Dec 3, 2021

0 votes

5

GATE CSE 1992 | Question: 12-b
Let the page reference and the working set window be $c\ c\ d\ b\ c\ e\ c\ e\ a\ d\ $ and $4$, respectively. The initial working set at time $t=0$ contains the pages $\{a,d,e\}$, where $a$ ... at time $t=-2$. Determine the total number of page faults and the average number of page frames used by computing the working set at each reference.

Let the page reference and the working set window be $c\ c\ d\ b\ c\ e\ c\ e\ a\ d\ $ and $4$, respectively. The initial working set at time $t=0$ contains the pages $\{a...

11.2k views

answered Nov 17, 2021

5 votes

6

GATE CSE 2021 Set 2 | Question: 48
Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below: The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)$ and page table entry size at every level is $8$ bytes. A ... $P$ across all levels is _________ $\text{KB}$.

Consider a three-level page table to translate a $39-$bit virtual address to a physical address as shown below:The page size is $\text{4 KB} \;(1\text{KB}=2^{10}$ bytes$)...

28.6k views

answered Nov 16, 2021

2 votes

7

GATE CSE 2005 | Question: 67
Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and the number of tag bits are respectively, $10, 17$ $10, 22$ $15, 17$ $5, 17$

Consider a direct mapped cache of size $32$ $KB$ with block size $32$ $bytes$. The $CPU$ generates $32$ $bit$ addresses. The number of bits needed for cache indexing and ...

15.2k views

answered Nov 12, 2021

1 votes

8

GATE CSE 2013 | Question: 20
In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. The lines in set $s$ are sequenced before the lines in set $(s+1)$. The main memory blocks are numbered 0 onwards. The ... $(j \text{ mod } k) * v \text{ to } (j \text{ mod } k) * v + (v-1) $

In a $k$-way set associative cache, the cache is divided into $v$ sets, each of which consists of $k$ lines. The lines of a set are placed in sequence one after another. ...

14.2k views

answered Nov 12, 2021

1 votes

9

GATE CSE 1999 | Question: 1.22
The main memory of a computer has $2\;\text{cm}$ blocks while the cache has $2\;\text{c}$ blocks. If the cache uses the set associative mapping scheme with $2$ blocks per set, then block $k$ of the main memory maps to the set: $(k \mod m)$ of the cache $(k \mod c)$ of the cache $(k \mod 2c)$ of the cache $(k \mod 2\; cm)$ of the cache

The main memory of a computer has $2\;\text{cm}$ blocks while the cache has $2\;\text{c}$ blocks. If the cache uses the set associative mapping scheme with $2$ blocks per...

7.7k views

answered Nov 12, 2021

0 votes

10

GATE CSE 1998 | Question: 18
For a set-associative Cache organization, the parameters are as follows: ... $1 \leq m \leq l$. Give the value of the hit ratio for $l = 1$.

For a set-associative Cache organization, the parameters are as follows:$$\begin{array}{|c|l|} \hline \text {$t _c$} & \text{Cache Access Time }\\\hline \text{$t _m$} &...

12.9k views

answered Nov 12, 2021

1 votes

11

GATE CSE 2006 | Question: 74
Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but direct mapped. The size of an address is $32\; \text{bits}$ in both cases . A $2\text{-to-}1$ multiplexer has ... The value of $h_1$ is: $2.4 \text{ ns} $ $2.3 \text{ ns}$ $1.8 \text{ ns}$ $1.7 \text{ ns}$

Consider two cache organizations. First one is $32 \; \textsf{KB}\;2\text{-way}$ set associative with $32 \; \text{byte}$ block size, the second is of same size but dire...

29.0k views

answered Nov 12, 2021

0 votes

12

GATE CSE 2006 | Question: 80
A CPU has a $32 KB$ direct mapped cache with $128$ byte-block size. Suppose A is two dimensional array of size $512 \times512$ with elements that occupy $8$-bytes each. Consider the following two C code segments, $P1$ and $P2$. P1: for (i=0; i<512; i++) { for (j=0; ... $P1$ be $M_{1}$and that for $P2$ be $M_{2}$. The value of $M_{1}$ is: $0$ $2048$ $16384$ $262144$

A CPU has a $32 KB$ direct mapped cache with $128$ byte-block size. Suppose A is two dimensional array of size $512 \times512$ with elements that occupy $8$-bytes each. C...

16.8k views

answered Nov 12, 2021

0 votes

13

GATE CSE 2014 Set 1 | Question: 44
An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses to the same block address is bounded above by $k$. What is the miss ratio if the access sequence is passed ... $\left(\dfrac{1}{N}\right)$ $\left(\dfrac{1}{A}\right)$ $\left(\dfrac{k}{n}\right)$

An access sequence of cache block addresses is of length $N$ and contains n unique block addresses. The number of unique block addresses between two consecutive accesses ...

22.7k views

answered Nov 12, 2021

1 votes

14

GATE CSE 2014 Set 2 | Question: 9
A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical address space is $4$ GB. The number of bits for the TAG field is ____

A $4$-way set-associative cache memory unit with a capacity of $16$ KB is built using a block size of $8$ words. The word length is $32$ bits. The size of the physical ad...

26.0k views

answered Nov 12, 2021

1 votes

15

GATE CSE 2014 Set 3 | Question: 44
The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write operation with a hit in cache and $10$ nanoseconds for a write ... cache hit-ratio is $0.9$. The average memory access time (in nanoseconds) in executing the sequence of instructions is ______.

The memory access time is $1$ nanosecond for a read operation with a hit in cache, $5$ nanoseconds for a read operation with a miss in cache, $2$ nanoseconds for a write ...

24.0k views

answered Nov 12, 2021

1 votes

16

GATE CSE 2011 | Question: 43
An $8\text{KB}$ direct-mapped write-back cache is organized as multiple blocks, each size of $32\text{-bytes}$. The processor generates $32\text{-bit}$ addresses. The cache controller contains the tag information for each cache block comprising of the ... the cache controller to store meta-data (tags) for the cache? $4864$ bits $6144$ bits $6656$ bits $5376$ bits

An $8\text{KB}$ direct-mapped write-back cache is organized as multiple blocks, each size of $32\text{-bytes}$. The processor generates $32\text{-bit}$ addresses. The cac...

12.4k views

answered Nov 12, 2021

2 votes

17

GATE CSE 2012 | Question: 54
A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ ... bit and $1$ replacement bit. The number of bits in the tag field of an address is $11$ $14$ $16$ $27$

A computer has a $256\text{-KByte}$, 4-way set associative, write back data cache with block size of $32\text{-Bytes}$. The processor sends $32\text{-bit}$ addresses to t...

22.1k views

answered Nov 12, 2021

1 votes

18

GATE CSE 2010 | Question: 48
A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cache is $16$ words. The memory access times are $2$ ... $L1$ cache. What is the time taken for this transfer? $2$ nanoseconds $20$ nanoseconds $22$ nanoseconds $88$ nanoseconds

A computer system has an $L1$ cache, an $L2$ cache, and a main memory unit connected as shown below. The block size in $L1$ cache is $4$ words. The block size in $L2$ cac...

42.6k views

answered Nov 11, 2021

1 votes

19

GATE CSE 1995 | Question: 2.25
A computer system has a $4 \ K$ word cache organized in block-set-associative manner with $4$ blocks per set, $64$ words per block. The number of bits in the SET and WORD fields of the main memory address format is: $15, 40$ $6, 4$ $7, 2$ $4, 6$

A computer system has a $4 \ K$ word cache organized in block-set-associative manner with $4$ blocks per set, $64$ words per block. The number of bits in the SET and WORD...

10.8k views

answered Nov 11, 2021

2 votes

20

GATE CSE 1996 | Question: 26
A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below: ... of less than $100 nsec$? What is the average access time achieved using the chosen sizes of level $1$ and level $2$ memories?

A computer system has a three-level memory hierarchy, with access time and hit ratios as shown below:$$\overset{ \text {Level $1$ (Cache memory)} \\ \text{Access time = ...

15.1k views

answered Nov 11, 2021

2 votes

21

GATE IT 2008 | Question: 80
Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1 \ MB$ of main memory, a word size of $1$ byte, a block size of $128$ words and a cache size of $8 \ KB$. The number of bits in the TAG, SET and WORD fields, respectively are: $7, 6, 7$ $8, 5, 7$ $8, 6, 6$ $9, 4, 7$

Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1 \ MB$ of main memory, a word size of $1$ byte, a block ...

7.0k views

answered Nov 11, 2021

1 votes

22

GATE IT 2008 | Question: 81
Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1\;\text{MB}$ of main memory, a word size of $1\;\text{byte}$, a block size of $128$ ... $000011000$ $110001111$ $00011000$ $110010101$

Consider a computer with a $4$-ways set-associative mapped cache of the following characteristics: a total of $1\;\text{MB}$ of main memory, a word size of $1\;\text{by...

5.8k views

answered Nov 11, 2021

0 votes

23

GATE IT 2007 | Question: 37
Consider a Direct Mapped Cache with 8 cache blocks (numbered $0-7$). If the memory block requests are in the following order $3, 5, 2, 8, 0, 63, 9,16, 20, 17, 25, 18, 30, 24, 2, 63, 5, 82,17, 24.$ Which of the following memory blocks will not be in the cache at the end of the sequence ? $3$ $18$ $20$ $30$

Consider a Direct Mapped Cache with 8 cache blocks (numbered $0-7$). If the memory block requests are in the following order$3, 5, 2, 8, 0, 63, 9,16, 20, 17, 25, 18, 30, ...

8.0k views

answered Nov 11, 2021

6 votes

24

GATE IT 2006 | Question: 42
A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is: $32$ $ns$ $64$ $ns$ $96$ $ns$ $128$ $ns$

A cache line is $64$ bytes. The main memory has latency $32$ $ns$ and bandwidth $1$ $GBytes/s$. The time required to fetch the entire cache line from the main memory is:$...

11.9k views

answered Nov 11, 2021

1 votes

25

GATE IT 2006 | Question: 43
A computer system has a level-$1$ instruction cache ($1$-cache), a level-$1$ data cache ($D$-cache) and a level-$2$ cache ($L2$-cache) with the following specifications: \begin{array}{|l|c|c|c|} \hline \text {} & \textbf{Capacity }& \textbf{Mapping Method} & \textbf{Block ... $18$-bit, $1$ K x $16$-bit $1$ K x $18$-bit, $512$ x $18$-bit, $1$ K x $18$-bit

A computer system has a level-$1$ instruction cache ($1$-cache), a level-$1$ data cache ($D$-cache) and a level-$2$ cache ($L2$-cache) with the following specifications:\...

7.2k views

answered Nov 11, 2021

0 votes

26

GATE IT 2004 | Question: 12, ISRO2016-77
Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rates of Level $1$ and Level $2$ caches are $0.8$ and $0.9$, respectively. What is the average access time of the system ignoring the search time within the cache? $13.0$ $12.8$ $12.6$ $12.4$

Consider a system with $2$ level cache. Access times of Level $1$ cache, Level $2$ cache and main memory are $1$ $ns$, $10$ $ns$, and $500$ $ns$ respectively. The hit rat...

29.6k views

answered Nov 11, 2021

0 votes

27

GATE IT 2005 | Question: 61
Consider a $2$-way set associative cache memory with $4$ sets and total $8$ cache blocks $(0-7)$ and a main memory with $128$ blocks $(0-127)$. What memory blocks will be present in the cache after the following sequence of memory block references if LRU policy is used for cache block replacement. ... $9$ $16$ $55$ $0$ $5$ $7$ $9$ $16$ $55$ $3$ $5$ $7$ $9$ $16$ $55$

Consider a $2$-way set associative cache memory with $4$ sets and total $8$ cache blocks $(0-7)$ and a main memory with $128$ blocks $(0-127)$. What memory blocks will be...

9.0k views

answered Nov 11, 2021

2 votes

28

GATE CSE 2015 Set 2 | Question: 24
Assume that for a certain processor, a read request takes $50\:\text{nanoseconds}$ on a cache miss and $5\:\text{nanoseconds}$ on a cache hit. Suppose while running a program, it was observed that $80\%$ of the processor's read requests result in a cache hit. The average read access time in nanoseconds is ______.

Assume that for a certain processor, a read request takes $50\:\text{nanoseconds}$ on a cache miss and $5\:\text{nanoseconds}$ on a cache hit. Suppose while running a pro...

13.9k views

answered Nov 11, 2021

1 votes

29

GATE CSE 2015 Set 3 | Question: 14
Consider a machine with a byte addressable main memory of $2^{20}$ bytes, block size of $16$ bytes and a direct mapped cache having $2^{12}$ cache lines. Let the addresses of two consecutive bytes in main memory be $\textsf{(E201F)}_{16}$ ... $\textsf{(E201F)}_{16}$? $\textsf{E, 201}$ $\textsf{F, 201}$ $\textsf{E, E20}$ $\textsf{2, 01F}$

Consider a machine with a byte addressable main memory of $2^{20}$ bytes, block size of $16$ bytes and a direct mapped cache having $2^{12}$ cache lines. Let the addresse...

8.6k views

answered Nov 11, 2021

0 votes

30

GATE CSE 2016 Set 2 | Question: 50
A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ ms and to read a block from the disk is $10$ ms. Assume that the cost ... in multiples of $10$ MB. The smallest cache size required to ensure an average read latency of less than $6$ ms is _________ MB.

A file system uses an in-memory cache to cache disk blocks. The miss rate of the cache is shown in the figure. The latency to read a block from the cache is $1$ ms and to...

15.0k views

answered Nov 11, 2021

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