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Answers by Mohnish
0
votes
1
GATE CSE 2007 | Question: 17
Consider the following statements about user level threads and kernel level threads. Which one of the following statements is FALSE? Context switch time is longer for kernel level threads than for user level threads. User level threads do ... be scheduled on different processors in a multi-processor system. Blocking one kernel level thread blocks all related threads.
Consider the following statements about user level threads and kernel level threads. Which one of the following statements is FALSE?Context switch time is longer for kern...
21.2k
views
answered
Feb 2, 2021
Operating System
gatecse-2007
operating-system
threads
normal
+
–
0
votes
2
GATE CSE 2014 Set 1 | Question: 12
Consider a rooted n node binary tree represented using pointers. The best upper bound on the time required to determine the number of subtrees having exactly $4$ nodes is $O(n^a\log^bn)$. Then the value of $a+10b$ is __________.
Consider a rooted n node binary tree represented using pointers. The best upper bound on the time required to determine the number of subtrees having exactly $4$ nodes is...
24.6k
views
answered
Jan 2, 2021
DS
gatecse-2014-set1
data-structures
binary-tree
numerical-answers
normal
+
–
0
votes
3
GATE CSE 2015 Set 2 | Question: 40
The number of onto functions (surjective functions) from set $X = \{1, 2, 3, 4\}$ to set $Y=\{a,b,c\}$ is ______.
The number of onto functions (surjective functions) from set $X = \{1, 2, 3, 4\}$ to set $Y=\{a,b,c\}$ is ______.
19.5k
views
answered
Dec 31, 2020
Set Theory & Algebra
gatecse-2015-set2
set-theory&algebra
functions
normal
numerical-answers
+
–
2
votes
4
GATE CSE 2003 | Question: 62
In a permutation $a_1\ldots a_n$, of $n$ distinct integers, an inversion is a pair $(a_i, a_j)$ such that $i < j$ and $a_i > a_j.$ What would be the worst case time complexity of the Insertion Sort algorithm, if the inputs are restricted to permutations of $1. . . n$ with at most $n$ inversions? $\Theta(n^2)$ $\Theta(n\log n)$ $\Theta(n^{1.5})$ $\Theta(n)$
In a permutation $a_1\ldots a_n$, of $n$ distinct integers, an inversion is a pair $(a_i, a_j)$ such that $i < j$ and $a_i a_j.$What would be the worst case time complex...
19.8k
views
answered
Dec 17, 2020
Algorithms
gatecse-2003
algorithms
sorting
normal
insertion-sort
+
–
1
votes
5
GATE CSE 2017 Set 1 | Question: 41
Consider a database that has the relation schemas EMP(EmpId, EmpName, DeptId), and DEPT(DeptName, DeptId). Note that the DeptId can be permitted to be NULL in the relation EMP. Consider the following queries on the database expressed in tuple relational calculus. { ... Which of the above queries are safe? I and II only I and III only II and III only I, II and III
Consider a database that has the relation schemas EMP(EmpId, EmpName, DeptId), and DEPT(DeptName, DeptId). Note that the DeptId can be permitted to be NULL in the relatio...
25.6k
views
answered
Dec 15, 2020
Databases
gatecse-2017-set1
databases
relational-calculus
safe-query
normal
+
–
3
votes
6
TIFR CSE 2014 | Part B | Question: 20
Consider the following game. There is a list of distinct numbers. At any round, a player arbitrarily chooses two numbers $a, b$ from the list and generates a new number $c$ by subtracting the smaller number from the larger one. The numbers $a$ and $b$ are put ... $273$. What is the score of the best player for this game? $40$ $16$ $33$ $91$ $123$
Consider the following game. There is a list of distinct numbers. At any round, a player arbitrarily chooses two numbers $a, b$ from the list and generates a new number $...
3.3k
views
answered
Dec 13, 2020
Algorithms
tifr2014
algorithms
identify-function
+
–
0
votes
7
GATE CSE 2009 | Question: 57, ISRO2016-75
Frames of $\text{1000 bits}$ are sent over a $10^6$ $\text{bps}$ duplex link between two hosts. The propagation time is $\text{25 ms}$. Frames are to be transmitted into this link to maximally pack them in transit (within the link). What is the ... ? Assume that no time gap needs to be given between transmission of two frames. $I=2$ $I=3$ $I=4$ $I=5$
Frames of $\text{1000 bits}$ are sent over a $10^6$ $\text{bps}$ duplex link between two hosts. The propagation time is $\text{25 ms}$. Frames are to be transmitted into ...
48.7k
views
answered
Dec 5, 2020
Computer Networks
gatecse-2009
computer-networks
sliding-window
normal
isro2016
+
–
10
votes
8
GATE CSE 2007 | Question: 47
Consider the process of inserting an element into a $Max \: Heap$, where the $Max \: Heap$ is represented by an $array$. Suppose we perform a binary search on the path from the new leaf to the root to find the position for the newly inserted element, the number of $comparisons$ performed is: $\Theta(\log_2n)$ $\Theta(\log_2\log_2n)$ $\Theta(n)$ $\Theta(n\log_2n)$
Consider the process of inserting an element into a $Max \: Heap$, where the $Max \: Heap$ is represented by an $array$. Suppose we perform a binary search on the path fr...
19.5k
views
answered
Nov 23, 2020
DS
gatecse-2007
data-structures
binary-heap
normal
+
–
1
votes
9
GATE2018 ME-1: GA-7
Given that $a$ and $b$ are integers and $a+a^2 b^3$ is odd, which of the following statements is correct? $a$ and $b$ are both odd $a$ and $b$ are both even $a$ is even and $b$ is odd $a$ is odd and $b$ is even
Given that $a$ and $b$ are integers and $a+a^2 b^3$ is odd, which of the following statements is correct?$a$ and $b$ are both odd$a$ and $b$ are both even$a$ is even and ...
1.3k
views
answered
Nov 2, 2020
Quantitative Aptitude
gate2018-me-1
general-aptitude
quantitative-aptitude
quadratic-equations
system-of-equations
+
–
0
votes
10
TIFR-2015-Maths-A-1
Let $A$ be an invertible $10 \times 10$ matrix with real entries such that the sum of each row is $1$. Then The sum of the entries of each row of the inverse of $A$ is $1$ The sum of the entries of each column of the inverse of $A$ is $1$ The trace of the inverse of $A$ is non-zero None of the above
Let $A$ be an invertible $10 \times 10$ matrix with real entries such that the sum of each row is $1$. ThenThe sum of the entries of each row of the inverse of $A$ is $1$...
2.1k
views
answered
Oct 29, 2020
Linear Algebra
tifrmaths2015
linear-algebra
matrix
+
–
0
votes
11
TIFR CSE 2018 | Part A | Question: 14
Let $A$ be an $n\times n$ invertible matrix with real entries whose row sums are all equal to $c$. Consider the following statements: Every row in the matrix $2A$ sums to $2c$. Every row in the matrix $A^{2}$ sums to $c^{2}$. Every row in ... and $(2)$ are correct but not necessarily statement $(3)$ all the three statements $(1), (2),$ and $(3)$ are correct
Let $A$ be an $n\times n$ invertible matrix with real entries whose row sums are all equal to $c$. Consider the following statements:Every row in the matrix $2A$ sums to ...
3.5k
views
answered
Oct 26, 2020
Linear Algebra
tifr2018
matrix
linear-algebra
+
–
0
votes
12
ISRO2020-30
Consider the following page reference string. $1\ 2\ 3\ 4\ 2\ 1\ 5\ 6\ 2\ 1\ 2\ 3\ 7\ 6\ 3\ 2\ 1\ 2\ 3\ 6\ $ What are the minimum number of frames required to get a single page fault for the above sequence assuming LRU replacement strategy? $7$ $4$ $6$ $5$
Consider the following page reference string.$1\ 2\ 3\ 4\ 2\ 1\ 5\ 6\ 2\ 1\ 2\ 3\ 7\ 6\ 3\ 2\ 1\ 2\ 3\ 6\ $What are the minimum number of frames required to get a single ...
5.5k
views
answered
Oct 5, 2020
Operating System
isro-2020
operating-system
memory-management
page-replacement
page-fault
normal
+
–
0
votes
13
why is the below state although being unsafe not leading to deadlock ?
I got the state to be unsafe since Available is (1,1) which can't satisfy the need of any process so why is not deadlock ?
I got the state to be unsafe since Available is (1,1) which can't satisfy the need of any process so why is not deadlock ?
866
views
answered
Sep 28, 2020
Operating System
resource-allocation
+
–
0
votes
14
GATE CSE 1999 | Question: 20-a
A certain processor provides a 'test and set' instruction that is used as follows: TSET register, flag This instruction atomically copies flag to register and sets flag to $1$. Give pseudo-code for implementing the entry and exit code to a critical region using this instruction.
A certain processor provides a 'test and set' instruction that is used as follows:TSET register, flagThis instruction atomically copies flag to register and sets flag to ...
4.5k
views
answered
Sep 26, 2020
Operating System
gate1999
operating-system
process-synchronization
normal
descriptive
+
–
0
votes
15
Operating system :- Starvation freedom and bounded wait
Starvation freedom => Bounded waiting ,this is a false implication as i have read,Can some one give any example proving this claim to be false?
Starvation freedom = Bounded waiting ,this is a false implication as i have read,Can some one give any example proving this claim to be false?
273
views
answered
Sep 17, 2020
Operating System
operating-system
+
–
0
votes
16
Simple Doubt in counting semaphore
Consider a non-negative counting semaphore S. During an execution, 16P (wait) operations, and 4V (signal) operations are issued in some order. The largest initial value of S for which at least three up operations will remain blocked is ___________ Can someone explain me the solution
Consider a non-negative counting semaphore S. During an execution, 16P (wait) operations, and 4V (signal) operations are issued in some order. The largest initial value o...
911
views
answered
Aug 18, 2020
Operating System
semaphore
binary-semaphore
+
–
1
votes
17
Self Doubt Context Switching Threads
S1: Context Switching occurs only in kernel mode. :TRUE S2: Context Switching in user mode is faster as compared to context switching in kernel mode. : TRUE If Context Switching occurs only in kernel mode, then how is CS in user mode faster ... switching and then change back to user mode which means more time should be taken as compared to CS in kernel mode.
S1: Context Switching occurs only in kernel mode. :TRUES2: Context Switching in user mode is faster as compared to context switching in kernel mode. : TRUEIf Context Swit...
3.0k
views
answered
Aug 10, 2020
Operating System
operating-system
context-switch
threads
+
–
0
votes
18
MadeEasy Test Series: Operating System - Process Schedule
Consider a uni-processor system executing four tasks T1, T2, T3, T4 each of which is composed of 10 sequence of jobs which arrive periodically at interval of 2, 4, 8, 16 ms resp. The priority of each task is directly ... Given all tasks initially arrive at t=0, the 2nd instance of T3 completes its execution at the end of ______ ms.
Consider a uni-processor system executing four tasks T1, T2, T3, T4 each of which is composed of 10 sequence of jobs which arrive periodically at interval of 2, 4, 8, 16 ...
1.0k
views
answered
Jul 20, 2020
Operating System
made-easy-test-series
operating-system
process-scheduling
+
–
0
votes
19
Process Scheduling
446
views
answered
Jul 18, 2020
Operating System
operating-system
process-scheduling
+
–
1
votes
20
Virtual Gate Test Series: CO & Architecture - Control Memory
In a $2$ level control unit design there exists $1K$ word micro control memory and a $32$ word nano control memory. If it is desired to provide $24$ control signals, what is the $\%the $ of reduction in ... control memory using nano programming with respect to the $1$ level control memory design? Explain what is nano programming$?$
In a $2$ level control unit design there exists $1K$ word micro control memory and a $32$ word nano control memory. If it is desired to provide $24$ control signals, what...
792
views
answered
Jul 10, 2020
CO and Architecture
co-and-architecture
microprogramming
virtual-gate-test-series
+
–
0
votes
21
Micro Instruction
Conditional bit(Flag) Micro-opn. Next Address Micro-Instruction Format If a micro program supports 46μ operations with a parallelism of 2,how many and what size of field exists in micro operation field? Given size of micro-opn field is 9bits. Answer: Total 9 bis divided in 4 and 5 bit. Can anyone explain how this division is being done.
Conditional bit(Flag)Micro-opn.Next Address Micro-Instruction FormatIf a micro program supports 46μ operations with a parallel...
2.4k
views
answered
Jul 10, 2020
CO and Architecture
microprogramming
co-and-architecture
control-unit
cpu
+
–
1
votes
22
Ace Test Series: CO & Architecture - DMA And Bus Architecture
Answer is D please explain
Answer is Dplease explain
546
views
answered
Jul 7, 2020
CO and Architecture
ace-test-series
co-and-architecture
dma
+
–
0
votes
23
Gateforum Tests
Can anybody explain in brief how to solve such numericals.
Can anybody explain in brief how to solve such numericals.
708
views
answered
Jul 3, 2020
CO and Architecture
co-and-architecture
interrupts
io-interface
+
–
0
votes
24
GATE CSE 1998 | Question: 25-a
Free disk space can be used to keep track of using a free list or a bit map. Disk addresses require $d$ bits. For a disk with $B$ blocks, $F$ of which are free, state the condition under which the free list uses less space than the bit map.
Free disk space can be used to keep track of using a free list or a bit map. Disk addresses require $d$ bits. For a disk with $B$ blocks, $F$ of which are free, state the...
5.3k
views
answered
May 21, 2020
Operating System
gate1998
operating-system
disk
descriptive
+
–
4
votes
25
GATE CSE 1992 | Question: 12-b
Let the page reference and the working set window be $c\ c\ d\ b\ c\ e\ c\ e\ a\ d\ $ and $4$, respectively. The initial working set at time $t=0$ contains the pages $\{a,d,e\}$, where $a$ ... at time $t=-2$. Determine the total number of page faults and the average number of page frames used by computing the working set at each reference.
Let the page reference and the working set window be $c\ c\ d\ b\ c\ e\ c\ e\ a\ d\ $ and $4$, respectively. The initial working set at time $t=0$ contains the pages $\{a...
11.2k
views
answered
May 13, 2020
Operating System
gate1992
operating-system
memory-management
normal
descriptive
+
–
0
votes
26
Minimum Number of tables for given ER-Diagram
2.6k
views
answered
Apr 19, 2020
Databases
er-diagram
databases
+
–
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