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Recent activity by Overflow04
1
answer
1
Algorithm
Answer ????
Answer ????
252
views
asked
Aug 13, 2023
Algorithms
algorithms
time-complexity
+
–
1
answer
2
Operating System
In Dining philosopher's problem, there are 8 number of diners and X number of chopsticks. What is the minimum value of X which ensures that therewill be no deadlock Note: Even number philosopher takes left fork first and odd number philosopher takes right fork first.
In Dining philosopher's problem, there are 8 number of diners and X number of chopsticks. What is the minimum value of X which ensures that therewill be no deadlock Note:...
562
views
commented
Jan 25, 2023
Operating System
operating-system
self-doubt
+
–
0
answers
3
Databases
Please explain option c.
Please explain option c.
247
views
asked
Jan 25, 2023
Databases
databases
test-series
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–
0
answers
4
COA
Which of the following is/are true for a CPU which does not have any stack pointer registers? A Interrupts are not possible. B All subroutine calls and interrupts are possible. C It cannot have nested subroutines call. D It cannot have subroutine call instruction.
Which of the following is/are true for a CPU which does not have any stack pointer registers?A Interrupts are not possible. B All subroutine calls and interrupts are po...
501
views
asked
Jan 24, 2023
CO and Architecture
co-and-architecture
self-doubt
interrupts
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–
1
answer
5
Programming
Someone please explain. Function of ‘^’
Someone please explain. Function of ‘^’
274
views
asked
Jan 24, 2023
Programming in C
programming-in-c
made-easy-test-series
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–
5
answers
6
GATE CSE 2003 | Question: 21
Consider the following graph: Among the following sequences: abeghf abfehg abfhge afghbe Which are the depth-first traversals of the above graph? I, II and IV only I and IV only II, III and IV only I, III and IV only
Consider the following graph: Among the following sequences:abeghfabfehgabfhgeafghbeWhich are the depth-first traversals of the above graph?I, II and IV onlyI and IV only...
13.2k
views
commented
Jan 15, 2023
Algorithms
gatecse-2003
algorithms
graph-algorithms
normal
graph-search
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–
1
answer
7
Operating System
When a page is referred for the first time, then it will be counted in page fault or not?. E.g page reference 1,2,3,4,2,1. LRU is used with 3 frames(initially empty).
When a page is referred for the first time, then it will be counted in page fault or not?.E.g page reference 1,2,3,4,2,1.LRU is used with 3 frames(initially empty).
690
views
asked
Jan 7, 2023
Operating System
operating-system
self-doubt
page-fault
+
–
5
answers
8
GATE CSE 2015 Set 3 | Question: 27
Assume that a mergesort algorithm in the worst case takes $30$ seconds for an input of size $64$. Which of the following most closely approximates the maximum input size of a problem that can be solved in $6$ minutes? $256$ $512$ $1024$ $2018$
Assume that a mergesort algorithm in the worst case takes $30$ seconds for an input of size $64$. Which of the following most closely approximates the maximum input size ...
20.1k
views
commented
Jan 3, 2023
Algorithms
gatecse-2015-set3
algorithms
sorting
+
–
1
answer
9
Programming
Why nothing is printed for %c.
Why nothing is printed for %c.
318
views
asked
Jan 3, 2023
Programming in C
programming
self-doubt
+
–
1
answer
10
Operating System
How c came into picture.
How c came into picture.
322
views
asked
Dec 31, 2022
Operating System
operating-system
counting
deadlock-prevention-avoidance-detection
test-series
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–
9
answers
11
GATE CSE 2005 | Question: 61
Consider line number $3$ of the following C-program. int main() { /*Line 1 */ int I, N; /*Line 2 */ fro (I=0, I<N, I++); /*Line 3 */ } Identify the compiler’s response about this line while creating the object-module: No compilation error Only a lexical error Only syntactic errors Both lexical and syntactic errors
Consider line number $3$ of the following C-program.int main() { /*Line 1 */ int I, N; /*Line 2 */ fro (I=0, I<N, I++); /*Line 3 */ }Identify the compiler’s response ab...
21.7k
views
commented
Dec 30, 2022
Compiler Design
gatecse-2005
compiler-design
compilation-phases
normal
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–
2
answers
12
GATE CSE 1992 | Question: 11b
Write $3$ address intermediate code (quadruples) for the following boolean expression in the sequence as it would be generated by a compiler. Partial evaluation of boolean expressions is not permitted. Assume the usual rules of precedence of the operators.$(a+b) > (c+d) \text{ or } a > c \text{ and }b < d$
Write $3$ address intermediate code (quadruples) for the following boolean expression in the sequence as it would be generated by a compiler. Partial evaluation of boolea...
2.7k
views
commented
Dec 30, 2022
Compiler Design
gate1992
compiler-design
syntax-directed-translation
intermediate-code
descriptive
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–
2
answers
13
GATE CSE 1988 | Question: 10ib
Consider the following grammar: $S \rightarrow S$ $S \rightarrow SS \mid a \mid \epsilon$ Indicate the shift-reduce and reduce-reduce conflict (if any) in the various states of the $\text{LR(0)}$ parser.
Consider the following grammar:$S \rightarrow S$$S \rightarrow SS \mid a \mid \epsilon$Indicate the shift-reduce and reduce-reduce conflict (if any) in the various states...
2.2k
views
commented
Dec 27, 2022
Compiler Design
gate1988
compiler-design
descriptive
grammar
parsing
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–
2
answers
14
GATE CSE 2004 | Question: 8
Which of the following grammar rules violate the requirements of an operator grammar? $P, Q, R$ are nonterminals, and $r, s, t$ are terminals. $P \rightarrow Q R$ $P \rightarrow Q s R$ $P \rightarrow \: \varepsilon$ $P \rightarrow Q t R r $ (I) only (I) and (III) only (II) and (III) only (III) and (IV) only
Which of the following grammar rules violate the requirements of an operator grammar? $P, Q, R$ are nonterminals, and $r, s, t$ are terminals.$P \rightarrow Q R$$P \right...
11.3k
views
commented
Dec 27, 2022
Compiler Design
gatecse-2004
compiler-design
grammar
normal
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–
1
answer
15
Algorithms
What is the logic applied here.
What is the logic applied here.
508
views
commented
Dec 26, 2022
Algorithms
algorithms
test-series
array
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–
2
answers
16
GATE IT 2007 | Question: 8
The following circuit implements a two-input AND gate using two $2-1$ multiplexers. What are the values of $X_1, X_2, X_3$? $X_1 = b, X_2 = 0, X_3 = a$ $X_1 = b, X_2 = 1, X_3 = b$ $X_1 = a, X_2 = b, X_3 = 1$ $X_1 = a, X_2 = 0, X_3 = b$
The following circuit implements a two-input AND gate using two $2-1$ multiplexers.What are the values of $X_1, X_2, X_3$?$X_1 = b, X_2 = 0, X_3 = a$$X_1 = b, X_2 = 1, X_...
7.6k
views
commented
Dec 22, 2022
Digital Logic
gateit-2007
digital-logic
normal
multiplexer
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–
5
answers
17
GATE CSE 2001 | Question: 2.11
Consider the circuit shown below. The output of a $2:1$ MUX is given by the function $(ac' + bc)$. Which of the following is true? $f=X_1'+X_2$ $f=X_1'X_2+X_1X_2'$ $f=X_1X_2+X_1'X_2'$ $f=X_1+X_2'$
Consider the circuit shown below. The output of a $2:1$ MUX is given by the function $(ac' + bc)$.Which of the following is true?$f=X_1'+X_2$$f=X_1'X_2+X_1X_2'$$f=X_1X_2+...
11.4k
views
commented
Dec 22, 2022
Digital Logic
gatecse-2001
digital-logic
normal
multiplexer
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–
0
answers
18
Operating System
Which of the following is correct? 1)In acyclic-graph directory, a file can have two different relative path name, but not two different absolute path name. 2)A dangling pointer possible for a file in tree-structured directories. 3)If Access Control List (ACL) ... directory, then size of a directory entry (with attributes) will be variable. 4)None of the above Answer given is 3
Which of the following is correct?1)In acyclic-graph directory, a file can have two different relative path name, but not two different absolute path name.2)A dangling po...
479
views
edited
Dec 16, 2022
Operating System
operating-system
test-series
file-system
+
–
4
answers
19
GATE CSE 2021 Set 2 | Question: 42
Consider the following multi-threaded code segment (in a mix of C and pseudo-code), invoked by two processes $P_1$ and $P_2$, and each of the processes spawns two threads $T_1$ and $T_2$: int x = 0; // global Lock L1; // global main () { create a ... the value of $y$ as $2.$ Both $T_1$ and $T_2$, in both the processes, will print the value of $y$ as $1.$
Consider the following multi-threaded code segment (in a mix of C and pseudo-code), invoked by two processes $P_1$ and $P_2$, and each of the processes ...
10.3k
views
commented
Dec 11, 2022
Operating System
gatecse-2021-set2
multiple-selects
operating-system
threads
2-marks
+
–
2
answers
20
GATE CSE 2001 | Question: 12
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or register) reads take place in the second phase of a clock cycle ... Show all data dependencies between the four instructions. Identify the data hazards. Can all hazards be avoided by forwarding in this case.
Consider a $5-$stage pipeline - IF (Instruction Fetch), ID (Instruction Decode and register read), EX (Execute), MEM (memory), and WB (Write Back). All (memory or registe...
18.0k
views
commented
Dec 5, 2022
CO and Architecture
gatecse-2001
co-and-architecture
pipelining
normal
descriptive
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–
3
answers
21
GATE CSE 2015 Set 2 | Question: 42
Consider a processor with byte-addressable memory. Assume that all registers, including program counter (PC) and Program Status Word (PSW), are size of two bytes. A stack in the main memory is implemented from memory location $(0100)_{16}$ and it grows upward. The stack ... value of the stack pointer is: $(016A)_{16}$ $(016C)_{16}$ $(0170)_{16}$ $(0172)_{16}$
Consider a processor with byte-addressable memory. Assume that all registers, including program counter (PC) and Program Status Word (PSW), are size of two bytes. A stack...
17.0k
views
commented
Dec 3, 2022
CO and Architecture
gatecse-2015-set2
co-and-architecture
machine-instruction
easy
+
–
4
answers
22
GATE CSE 2009 | Question: 8, UGCNET-June2012-III: 58
A CPU generally handles an interrupt by executing an interrupt service routine: As soon as an interrupt is raised. By checking the interrupt register at the end of fetch cycle. By checking the interrupt register after finishing the execution of the current instruction. By checking the interrupt register at fixed time intervals.
A CPU generally handles an interrupt by executing an interrupt service routine:As soon as an interrupt is raised.By checking the interrupt register at the end of fetch cy...
15.9k
views
commented
Dec 3, 2022
CO and Architecture
gatecse-2009
co-and-architecture
interrupts
normal
ugcnetcse-june2012-paper3
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–
7
answers
23
GATE CSE 2018 | Question: 5
Consider the following processor design characteristics: Register-to-register arithmetic operations only Fixed-length instruction format Hardwired control unit Which of the characteristics above are used in the design of a RISC processor? I and II only II and III only I and III only I, II and III
Consider the following processor design characteristics:Register-to-register arithmetic operations onlyFixed-length instruction formatHardwired control unitWhich of the c...
12.0k
views
commented
Dec 2, 2022
CO and Architecture
gatecse-2018
co-and-architecture
cisc-risc-architecture
easy
1-mark
+
–
0
answers
24
Databases
How to identify many to many relationship. Can R2 be one to one.
How to identify many to many relationship.Can R2 be one to one.
334
views
commented
Nov 29, 2022
Databases
test-series
databases
relational-model
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–
1
answer
25
Databases
In Query1, how mid is projected from did.?????????/
In Query1, how mid is projected from did.?????????/
248
views
asked
Nov 29, 2022
Databases
databases
test-series
+
–
1
answer
26
GATE CSE 2002 | Question: 22
Construct all the parse trees corresponding to $i + j * k$ for the grammar $E \rightarrow E+E$ $E \rightarrow E*E$ $E \rightarrow id$ In this grammar, what is the precedence of the two operators $*$ and $+$? If only one parse tree is desired for any string in the same language, what changes are to be made so that the resulting LALR(1) grammar is unambiguous?
Construct all the parse trees corresponding to $i + j * k$ for the grammar $E \rightarrow E+E$ $E \rightarrow E*E$ $E \rightarrow id$In this grammar, what is the pr...
3.9k
views
commented
Nov 28, 2022
Compiler Design
gatecse-2002
compiler-design
parsing
normal
descriptive
+
–
0
answers
27
Computer Networks
Number of packets readily available in the buffer are 10. 4 bit sequence number is used. The maximum number of outstanding frames are Answer given is: 10
Number of packets readily available in the buffer are 10.4 bit sequence number is used. The maximum number of outstanding frames areAnswer given is: 10
390
views
asked
Nov 28, 2022
Computer Networks
computer-networks
test-series
+
–
1
answer
28
Computer Networks
I am getting M1 as correct.
I am getting M1 as correct.
409
views
commented
Nov 19, 2022
Computer Networks
computer-networks
test-series
ip-address
+
–
1
answer
29
Computer Networks
Since 8 bit delimeter pattern = 01111110. So whenever 0111111( 6’s ones) is matched we will add one extra bit. But in the solution extra bit is added just after 011111(5’s ones).
Since 8 bit delimeter pattern = 01111110. So whenever 0111111( 6’s ones) is matched we will add one extra bit.But in the solution extra bit is added just after 011111...
315
views
asked
Nov 18, 2022
Computer Networks
computer-networks
test-series
+
–
0
answers
30
Computer Networks
What is the significance of this line(highlighted part): Node D get this flood packet from nodes C, F,B,E in this order. Other things are clear to me.
What is the significance of this line(highlighted part): Node D get this flood packet from nodes C, F,B,E in this order.Other things are clear to me.
368
views
asked
Nov 18, 2022
Computer Networks
computer-networks
routers-bridge-hubs-switches
test-series
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