Recent activity by PAVANCHYTANYA / GATE Overflow for GATE CSE

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GATE CSE 2020 | Question: 43
Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this processor. Overheads associated with pipelining force you to ... , the speedup achieved by the pipelined processor over the non-pipelined processor (round off to $2$ decimal places) is_____________.

Consider a non-pipelined processor operating at $2.5$ GHz. It takes $5$ clock cycles to complete an instruction. You are going to make a $5$- stage pipeline out of this p...

16.5k views

commented Oct 25, 2022

2 answers

2

GATE CSE 2022 | Question: 44
Consider a system with $2 \;\text{KB}$ direct mapped data cache with a block size of $64 \; \text{bytes}.$ The system has a physical address space of $64 \; \text{KB}$ and a word length of $16 \; \text{bits.}$ During the execution of a program, four data ... only $\text{R}$ and $\text{S}$ reside in the cache. Every access to $\text{R}$ evicts $\text{Q}$ from the cache.

Consider a system with $2 \;\text{KB}$ direct mapped data cache with a block size of $64 \; \text{bytes}.$ The system has a physical address space of $64 \; \text{KB}$ an...

9.1k views

commented Oct 23, 2022

3 answers

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GATE IT 2004 | Question: 47
Consider a pipeline processor with $4$ stages $S1$ to $S4$. We want to execute the following loop: for (i = 1; i < = 1000; i++) {I1, I2, I3, I4} where the time taken (in ns) by instructions $I1$ to $I4$ for stages $S1$ to $S4$ ... output of $I1$ for $i = 2$ will be available after $\text{11 ns}$ $\text{12 ns}$ $\text{13 ns}$ $\text{28 ns}$

Consider a pipeline processor with $4$ stages $S1$ to $S4$. We want to execute the following loop:for (i = 1; i < = 1000; i++) {I1, I2, I3, I4}where the time taken (in ns...

12.5k views

commented Aug 17, 2022

12 answers

4

GATE CSE 2005 | Question: 80
Consider the following data path of a $\text{CPU}.$ The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including incrementation of the $\text{PC}$ and the $\text{GPRs}$ are to be carried out in ... $2$ $3$ $4$ $5$

Consider the following data path of a $\text{CPU}.$The $\text{ALU},$ the bus and all the registers in the data path are of identical size. All operations including increm...

24.2k views

commented Aug 11, 2022

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