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User Parth Shah
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Recent activity by Parth Shah
9
answers
1
GATE CSE 2004 | Question: 21, ISRO2007-44
The minimum number of page frames that must be allocated to a running process in a virtual memory environment is determined by the instruction set architecture page size number of processes in memory physical memory size
comment edited
in
Operating System
Oct 2, 2020
18.0k
views
gatecse-2004
operating-system
virtual-memory
page-replacement
normal
isro2007
6
answers
2
GATE IT 2005 | Question: 28
Which of the following statements is FALSE regarding a bridge? Bridge is a layer $2$ device Bridge reduces collision domain Bridge is used to connect two or more LAN segments Bridge reduces broadcast domain
commented
in
Computer Networks
Mar 2, 2020
7.5k
views
gateit-2005
computer-networks
lan-technologies
normal
1
answer
3
Regular expressions
commented
in
Theory of Computation
Mar 31, 2019
492
views
theory-of-computation
regular-expression
regular-language
5
answers
4
GATE CSE 2004 | Question: 32
Consider the following program fragment for reversing the digits in a given integer to obtain a new integer. Let $n = d_1\, d_2\, \ldots\, d_m$. int n, rev; rev = 0; while(n > 0) { rev = rev * 10 + n%10; n = n/10; } The loop invariant condition at the end ... $n=d_1\, d_2 \,\ldots\, d_m \qquad \mathbf{or} \qquad \text{rev} =d_m \,\ldots\, d_2\, d_1$
commented
in
Programming
Feb 22, 2019
8.4k
views
gatecse-2004
programming
loop-invariants
normal
4
answers
5
GATE CSE 2017 Set 1 | Question: 31
Let $A$ be $n\times n$ real valued square symmetric matrix of rank $2$ with $\sum_{i=1}^{n}\sum_{j=1}^{n}A^{2}_{ij} = 50.$ Consider the following statements. One eigenvalue must be in $\left [ -5,5 \right ]$ The eigenvalue ... than $5$ Which of the above statements about eigenvalues of $A$ is/are necessarily CORRECT? Both I and II I only II only Neither I nor II
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in
Linear Algebra
Jan 16, 2019
18.9k
views
gatecse-2017-set1
linear-algebra
eigen-value
normal
1
answer
6
doubt
Overlaying is used to run a program which is longer than the address space of a computer Is the above statement is TRUE/FALSE? I think it is TRUE, as we can load required process space for execution at different time. Correct me if I am wrong
commented
in
Operating System
Jan 8, 2019
563
views
operating-system
overlay
2
answers
7
MadeEasy Test Series: CO & Architecture - IO Handling
A CPU scans the status of output I/O device every 20ms. The interface for the I/O device includes two different parts one for status and other for data output. Assume the clock rate of CPU is 8MHz and every instruction takes 10 cycles. What is the time taken(in microseconds) to scan and service the I/O device by CPU? A)4.5 B)3.75 C)1.25 D)2.5
asked
in
CO and Architecture
Jan 7, 2019
495
views
made-easy-test-series
co-and-architecture
io-handling
2
answers
8
MADE EASY 2018 - ICMP
Consider a very large network of 10000 routers.Two host A and B are connected to this network,host A sends data to host B and after some unit of time host A receives ICMP time exceeded message for the same data packet. The maximum number of routers that can be travelled by packets when ICMP message reaches back to HOST A ?
answered
in
Computer Networks
Jan 7, 2019
696
views
computer-networks
icmp
madeeasy-testseries-2018
3
answers
9
Digital Logic: Gate2016 ECE
The delays of NOR gates, Multiplexer and Inverters are 2ns, 1.5ns and 1ns respectively. If all the inputs P, Q, R, S and T are applied at the same time instant, Then the Maximum propagation delay (in ns) of the circuit is _______________
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in
Digital Logic
Jan 7, 2019
4.6k
views
multiplexer
gate-ece
digital-logic
4
answers
10
GATE IT 2008 | Question: 78
A CFG $G$ is given with the following productions where $S$ is the start symbol, $A$ is a non-terminal and $a$ and $b$ are terminals. $S \to aS \mid A$ $A \to aAb \mid bAa \mid \epsilon$ Which of the following strings is generated by the grammar above? $aabbaba$ $aabaaba$ $abababb$ $aabbaab$
commented
in
Compiler Design
Jan 6, 2019
6.6k
views
gateit-2008
parsing
normal
context-free-language
3
answers
11
Gateforum Test Series: Databases - Transactions
Which of the following is false? a)All the schedules which are allowed under basic time stamp ordering protocols are also allowed under Thomas write rule. b)Schedules which are allowed under Thomas write rule are also allowed under ... are not allowed Thomas write rule are also not allowed in a multi-version timestamp ordering protocol. d)None.
commented
in
Databases
Jan 5, 2019
3.9k
views
databases
gateforum-test-series
transaction-and-concurrency
5
answers
12
GATE CSE 2018 | Question: 26
Consider a matrix P whose only eigenvectors are the multiples of $\begin{bmatrix} 1 \\ 4 \end{bmatrix}$. Consider the following statements. P does not have an inverse P has a repeated eigenvalue P cannot be diagonalized Which one of the ... III are necessarily true Only II is necessarily true Only I and II are necessarily true Only II and III are necessarily true
commented
in
Linear Algebra
Jan 5, 2019
18.7k
views
gatecse-2018
linear-algebra
matrix
eigen-value
normal
3
answers
13
GATE CSE 2014 Set 3 | Question: 4
Which one of the following statements is TRUE about every $n \times n$ matrix with only real eigenvalues? If the trace of the matrix is positive and the determinant of the matrix is negative, at least one of its eigenvalues is ... eigenvalues are positive. If the product of the trace and determinant of the matrix is positive, all its eigenvalues are positive.
answered
in
Linear Algebra
Jan 5, 2019
8.5k
views
gatecse-2014-set3
linear-algebra
eigen-value
normal
3
answers
14
GATE CSE 1991 | Question: 01,xiv
If the longest chain in a partial order is of length $n$, then the partial order can be written as a _____ of $n$ antichains.
commented
in
Set Theory & Algebra
Dec 29, 2018
4.0k
views
gate1991
set-theory&algebra
partial-order
normal
fill-in-the-blanks
3
answers
15
GATE CSE 2018 | Question: 24
Consider a system with $3$ processes that share $4$ instances of the same resource type. Each process can request a maximum of $K$ instances. Resources can be requested and releases only one at a time. The largest value of $K$ that will always avoid deadlock is ___
commented
in
Operating System
Dec 23, 2018
13.7k
views
gatecse-2018
operating-system
deadlock-prevention-avoidance-detection
easy
numerical-answers
0
answers
16
MadeEasy Subject Test 2019: Digital Logic - Flip Flop
A traffic signal cycles from RED to YELLOW, YELLOW to GREEN and GREEN to RED. In each cycle RED is turned for 100 seconds, YELLOW is turned for 40 seconds and GREEN is turned for 80 seconds. The traffic has to be implemented using ... to this FSM is a clock of 10 second period. The minimum number of flip-flops required to implement this FSM is?
commented
in
Digital Logic
Dec 23, 2018
995
views
made-easy-test-series
digital-logic
flip-flop
3
answers
17
GATE CSE 2015 Set 2 | Question: 30
Consider $6$ memory partitions of sizes $200$ $\text{KB}$, $400$ $\text{KB}$, $600$ $\text{KB}$, $500$ $\text{KB}$, $300$ $\text{KB}$and $250$ $\text{KB}$, where $\text{KB}$refers to $\text{kilobyte}$. These partitions need to be allotted to four processes of ... and $250$ $\text{KB}$ $250$ $\text{KB}$ and $300$ $\text{KB}$ $300$ $\text{KB}$ and $400$ $\text{KB}$
commented
in
Operating System
Dec 19, 2018
5.5k
views
gatecse-2015-set2
operating-system
memory-management
easy
2
answers
18
Gateforum Test Series: Programming & DS - Binary Tree
Suppose binary tree has only three nodes A,B and C, and you are given the post order traversal of tree as B-A-C . The exact pre order traversal of the tree is? A)C-A-B B)A-B-C C)C-B-A D)Can't be determined from given information.
commented
in
DS
Dec 12, 2018
862
views
gateforum-test-series
data-structures
binary-tree
0
answers
19
Gateforum Test Series: Digital Logic - Digital Counter
The circuit shown in figure is using one 4-bit BCD counter and one 4-bit binary counter. The MOD value for the counter is ?
commented
in
Digital Logic
Dec 11, 2018
362
views
gateforum-test-series
digital-logic
digital-counter
0
answers
20
Gateforum Test Series: Digital Logic - Digital Counter
The MOD value (or) number of states in the ripple counter as shown in the figure is? Answer given: Mod 7 counter. My doubt is that won't it go till 111 and then the counter is cleared as the input to NAND gate is taken from the output of the flipflops?
asked
in
Digital Logic
Dec 11, 2018
121
views
gateforum-test-series
digital-logic
digital-counter
1
answer
21
Gateforum Test Series: Programming & DS - Programming In C
Which of the statements are false about keyword register'? Register keyword can be used with a pointer variable as register can have address of memory location. We can use '&' operator with register variable and access address of ... of the above D) both b and c. Can someone explain the choice a more clearly in the above question?
commented
in
Programming
Nov 29, 2018
181
views
gateforum-test-series
programming-in-c
programming
1
answer
22
GATE CSE 1990 | Question: 16a
Show that grammar $G_1$ is ambiguous using parse trees: $G_{1}: S \rightarrow$ if $S$ then $S$ else $S$ $S \rightarrow$ if $S$ then $S$
commented
in
Compiler Design
Nov 28, 2018
5.5k
views
gate1990
descriptive
compiler-design
grammar
3
answers
23
decidability-toc
Which of the following is not decidable problem? (a) A sting is generated by C.N.F or Not? (b) A given non-terminal A in a given grammar CFG is ever used in the generation of word (c) Given context-free Grammar generates an infinite language or a finite language (d) None of the above
commented
in
Theory of Computation
Nov 16, 2018
1.4k
views
gateforum-test-series
theory-of-computation
decidability
0
answers
24
Gateforum Test Series: Theory of Computation - Context Free Languages
Consider the following CFG, find the number of production in the minimized grammar after it was converted to Greibach Normal Form. S->AA|0 A->SS|1
asked
in
Theory of Computation
Nov 16, 2018
112
views
gateforum-test-series
theory-of-computation
context-free-language
2
answers
25
Gateforum Test Series: Computer Networks - Lan Technologies
Let cluster of stations share 48kbps of pure aloha channel. Every station outputs frame of length 1024 bit in every 50 seconds. Then what is the maximum value of number of stations?
commented
in
Computer Networks
Nov 5, 2018
445
views
gateforum-test-series
computer-networks
lan-technologies
0
answers
26
#Self Doubt
Consider the following statements: S1: Packet switching is faster than circuit switching. S2: In synchronous serial transfer synchronous bits are treated as part of data. a) S1 is true and S2 is false. b) S1 is false and S2 is true. c) both S1 and S2 are true. d) both S1 and S2 are false.
asked
in
Computer Networks
Nov 1, 2018
105
views
computer-networks
1
answer
27
MadeEasy Test Series: Operating System - Process Synchronization
What is the main reason for RACE condition while synchronzing the process? A)The two processes trying to update the variable at same time. B) More than one process entering into the critical section at same time. C)Mutual Exclusion condition not satisfies. D)All of the above
commented
in
Operating System
Nov 1, 2018
730
views
operating-system
process-synchronization
made-easy-test-series
2
answers
28
GATE CSE 1987 | Question: 1-vii
The exponent of a floating-point number is represented in excess-$\text{N}$ code so that: The dynamic range is large. The precision is high. The smallest number is represented by all zeros. Overflow is avoided.
commented
in
Digital Logic
Sep 2, 2018
3.8k
views
gate1987
digital-logic
number-representation
floating-point-representation
2
answers
29
TOC:- Chomsky hierarchy
Where does NP hard / NP complete problems fits in the Chomsky hierarchy ? Is there any relation of Np hard problems with RE languages?
answered
in
Theory of Computation
Sep 2, 2018
710
views
theory-of-computation
grammar
3
answers
30
GATE IT 2006 | Question: 36
The majority function is a Boolean function $f(x, y, z)$ that takes the value $1$ whenever a majority of the variables $x,y,z$ are $1.$ In the circuit diagram for the majority function shown below, the logic gates for the boxes labeled $P$ and $Q$ are, ... $\textsf{XOR}, \textsf{XOR}$ $\textsf{OR}, \textsf{OR}$ $\textsf{OR}, \textsf{AND}$
answered
in
Digital Logic
Sep 1, 2018
7.1k
views
gateit-2006
digital-logic
circuit-output
normal
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