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Questions by Prajwal Bhat
User Prajwal Bhat
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User Prajwal Bhat
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+1
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0
answers
1
TOC  Micheal Sipser  Regular languages
asked
Oct 24
in
Theory of Computation

47
views
theoryofcomputation
regularlanguages
closureproperty
0
votes
3
answers
2
No. of DFA's Possible
The number of different DFA's with two states X and Y,where X is the initial state,over the alphabet $\sum$ = {0,1,2}
asked
Feb 4
in
Theory of Computation

189
views
finiteautomata
counting
+2
votes
1
answer
3
Stacks and Permutation
A stack A has 4 entries as following sequence a,b,c,d and stack B is empty. An entry popped out of stack A can be printed or pushed to stack B. An entry popped out of stack B can only be printed. Then the number of possible permutations that the entries can be printed will be ? Stack A Stack B = empty a(TOP) b c d
asked
Feb 3
in
DS

444
views
permutationsandcombinations
discretemathematics
datastructure
+1
vote
0
answers
4
Recursive relation
What does this problem tells and how it is related to Fibonacci series? Couldn't understand the question
asked
Jan 29
in
Combinatory

64
views
recurrence
+2
votes
2
answers
5
Pipeline
Assume that execution of 200 instructions on a 6 staged pipeline where the target address is available at 4th stage.Let X be the probability of an instruction not being branch. The value of X such that speedup is atleast 5 is?
asked
Jan 22
in
CO & Architecture

296
views
coandarchitecture
pipelining
stall
+1
vote
1
answer
6
Minimum No of states in DFA
No. of states in the DFA accepting the following set of strings are: ( ( aa* + φ* )* (aa* + φ* ) + bb* + φ* φ + φ* )* Quite confusing to me. Share your approach!
asked
Jan 17
in
Theory of Computation

284
views
theoryofcomputation
minimalstateautomata
dfa
theoryofcomputation_
finiteautomata
+7
votes
1
answer
7
LL(k) grammars
1. LL(k) grammars have one to one correspondance with DCFL's 2. LR(k) grammars have one to one correspondance with CFL's Which of them is True and explain it bit clearly?
asked
Jan 15
in
Compiler Design

693
views
theoryofcomputation
compilerdesign
grammar
ll1
+2
votes
1
answer
8
Pipeline
An instruction pipeline has stages as given in diagram A program consistsing of 9 instruction I1,I2....I9 is executed in this pipeline processor.instruction I3 is the only conditional branch instruction and its branch target is I7,If the branch taken after EI state,the time needed to complete the program is?
asked
Jan 14
in
CO & Architecture

151
views
coandarchitecture
pipelining
+2
votes
1
answer
9
CNTCP
Assume a new TCP connection starts by sending 1 segment and then increases it congestion windows by 1 segment each time it receives an acknowledgement i,e after 1RTT congestion window is 2 segments in slowstart.Assume connection never leaves slow start.Find the number of RTT's it takes to send N segments Given ans is Log2(N+1)
asked
Jan 13
in
Computer Networks

205
views
computernetworks
tcp
congestioncontrol
+3
votes
5
answers
10
Probability
2 friends Alice and Bob have found an unfair coin,It has 72% chance of coming up heads.Alice and Bob plays a game with this coin.If coin comes up head then tails,Alice wins.If it's reverse(tails,then heas),Bob wins.And if neither of those two things happens,the game restarts and continues untill there is a winner What is Bob's probability of winning?
asked
Jan 12
in
Mathematical Logic

282
views
probability
engineeringmathematics
+2
votes
2
answers
11
Generating Function
Find the coefficient of x83 in (x5+ x8+ x11+ x14+ x17)10 ?
asked
Jan 11
in
Combinatory

429
views
generatingfunctions
permutationsandcombinations
+3
votes
1
answer
12
CN TCP
Imagine a TCP connection is transferring 6000B. First Byte is numbered as 10010.The sequence number of the last byte sent,if data are sent in 5 segments with the first 4 segments carrying 1000B and last segement carrying 2000B are ?
asked
Jan 11
in
Computer Networks

201
views
tcp
computernetworks
+3
votes
3
answers
13
CO Cache stall cycles
Suppose that in 500 memory references there are 50 misses in the first level cache and 20 misses in the second level cache.Assume miss penalty from the L2 cache to memory is 100 cycles.The hit time of L2 cache is 20 cycle. ... is 10 cycles. If there are 2.5 memory references per instruction.How many average stall cycles per instructions are there?
asked
Jan 7
in
CO & Architecture

391
views
coandarchitecture
stall
cycle
cachememory
+1
vote
2
answers
14
CNTCP Congestion control
Consider the effect of using slow start on a line with propagation delay of 10ms.The receive window is 24KB and the maximum segment size is 2KB.How long does it take to send full window size segment in ms initial threshold of 20KB? My ans is 2  4  8  16 ... 24  Thus 8 RTT's= 160ms Given ans is 2  4  8  16  20  24  Thus 6 RTT's =120ms
asked
Jan 6
in
Computer Networks

302
views
computernetworks
congestioncontrol
tcp
0
votes
1
answer
15
TOC Recurive language
R = RE ∩ CoRE where R is the set of recursive language,RE is the set of languages of which membership can be proved in finite time and CoRE is the set of language of which membership can be disproved in finite amount of time True/False?
asked
Jan 6
in
Theory of Computation

23
views
theoryofcomputation
recursiveandrecursivelyenumerablelanguages
+1
vote
0
answers
16
Undecidability
REVERSE = { M  M is a TM with the property: for all w, M(w) accepts iff M(wR) accepts} Here getting confused for applying condition to apply Rice's theorem for the given property Tyes={Palindromes} Tno={Nonpalindromes} Because of ... correct here ? and is it Turing Recognisable ?can we apply Rice's 2nd theorem? Source:https://goo.gl/UIhNyT (Problem 1)
asked
Jan 2
in
Theory of Computation

59
views
theoryofcomputation
decidability
0
votes
1
answer
17
Pipeline GATE200928
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 I1 S1 S1 S2 S3 S4 I2 S1 S2 S2 S2 S3 S3 S4 S4 I3 S1 S1 X S2 X S3 X S4 S4 S4 I4 S1 X S2 S2 S3 S3 X S4 S4 I1 S1 S1 S2 X X S3 X S4 ... S2 S2 S3 S3 X S4 S4 Given ans is 23 and my ans 25.Where i'm going wrong? It is also gate previous year question :https://gateoverflow.in/1314/gate200928
asked
Dec 31, 2016
in
CO & Architecture

434
views
pipelining
coandarchitecture
virtualgate
+3
votes
1
answer
18
Combinatorics
The answer given is nk+1C2 but couldn't understand how both are related
asked
Dec 29, 2016
in
Combinatory

109
views
permutationsandcombinations
discretemathematics
+1
vote
0
answers
19
Page Replacement Algorithm #Virtualgate
asked
Dec 27, 2016
in
Operating System

188
views
pagefault
operatingsystem
pagereplacement
+2
votes
1
answer
20
#Selfdoubt Rice's Theorem
What is the difference between Nontrivial property (in 1st theorem)and Nonmonotonic property ( in 2nd theorem)? I was going through Rice's theorem but unable to differentiate between these 2 properties.Please give the detail to differentiate both ... language of other (Tno) and L(Tyes)⊂L(Tno) Source: http://gatecse.in/ricestheorem/
asked
Dec 26, 2016
in
Theory of Computation

250
views
theoryofcomputation
ricetheorem
decidability
0
votes
1
answer
21
DMA Cycle stealing
Explain in detail?
asked
Dec 21, 2016
in
CO & Architecture

221
views
dma
coandarchitecture
0
votes
0
answers
22
Heapsort #Virtualgate
Need approach to solve this ?
asked
Dec 20, 2016
in
Algorithms

132
views
heapsort
algorithms
+4
votes
2
answers
23
Expanding opcode technique
A CPU is designed to have 58 threeaddress instructions and 25 twoaddress instructions. The CPU is able to address a maximum of 16 memory locations. The length of machine code is the same for all instructions. If ... instructions iv) Determine the length of the machine code v) List the machine codes Detailed explanation would be helpful
asked
Dec 10, 2016
in
CO & Architecture

1.1k
views
coandarchitecture
machineinstructions
0
votes
2
answers
24
OS Doubt
Need explanation of Long term Scheduler , Short term Scheduler and Medium term scheduler Please give me the detailed explanation since many websites are defining each of these in their own way
asked
Nov 20, 2016
in
Operating System

128
views
operatingsystem
cpuscheduling
processschedule
+3
votes
1
answer
25
TestBook Tests Digital logic
Let X be the number of AND gates required and Y be the number of OR gates required in 4bit Carry lookahead adder . Then what is value of 2X+2Y? My doubt here is they are just talking about AND and OR gate but usually we use ... well as XOR gate in CLA adder, Do we need to expand XOR gate and consider the AND and OR gate? Please Explain ?
asked
Nov 14, 2016
in
Digital Logic

190
views
digitallogic
digitalcircuits
combinational
testbooktestseries
+2
votes
1
answer
26
Discrete Maths
Messages are transmitted through a communication channel using two signals. The transmission of one signal requires $1 $ microsecond, the transmission of other signal requires $2$ microseconds. Assume that each signal in a message is immediately followed by the ... of these two signals that can be sent in $10 \mu s$ is _________ ? Please explain ...?
asked
Nov 11, 2016
in
Combinatory

246
views
fibonaccisequenceapplication
permutationsandcombinations
+1
vote
1
answer
27
Trees
There are nn2 labeled trees with n vertices(n>2) Can anyone explain it with complete proof?
asked
Oct 16, 2016
in
Programming

132
views
trees
graphtheory
+2
votes
1
answer
28
#View Serializability #DBMS
I know that this is Conflict serializable and i know all schedules which are Conflict serializable are also view serializable But still wanted to know what is the view serializable sequence?
asked
Sep 5, 2016
in
Databases

188
views
view_serializable
databases
transactions
+3
votes
1
answer
29
Testbook test series #BigOh
asked
Aug 26, 2016
in
Algorithms

184
views
testseries
timecomplexity
algorithms
0
votes
1
answer
30
What is the Output?
#include<stdio.h> int main() { int a = 10, b = 20, c = 30, d = 40; printf("%d%d%d",a, b, c); printf("%d%d%d", d); return 0; } What is the Output and when I run it I am getting some wierd answer. Please explain ?
asked
Aug 20, 2016
in
Programming

183
views
programminginc
undefinedbehaviour
output
nongate
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